JPWO2005125019A1 - Turbo code error correction decoding method and turbo code error correction decoding apparatus - Google Patents

Abstract

A code length N turbo code reception sequence is separated into an information bit sequence, a check bit sequence 1 corresponding to an uninterleaved encoder, and a check bit sequence 2 corresponding to an interleaved encoder. In the error correction decoding method of turbo code that performs soft input / soft output decoding processing by calculating a reverse path metric and a forward path metric for each divided block, and for each separated sequence A selection is made for each M symbols from the top to form one block, which is divided into K blocks, the block length from block 1 to block (K-1) is made up of M symbols, and the block of the last block K A turbo code error correction decoding method having a length of (N−M (K−1)) symbols.

Description

  The present invention relates to an error correction code used in the communication field, and more particularly to an error correction decoding method for a turbo code and an error correction decoding device for a turbo code.

  In a conventional turbo code error correction decoding method, as shown in, for example, Japanese Patent Laid-Open No. 2002-204173, in a method in which a received sequence is decoded using a maximum a posteriori algorithm, reverse processing is performed for a certain length. Thereafter, the first result value by reverse processing is calculated and stored, and the second result value by forward processing is calculated simultaneously with the learning time, and the second result value and the first result value are calculated. The decoding output is determined using the first result value stored before one result value.

Here, assuming that the length of the backward or forward processing is W, the learning length is L, and the remainder obtained by dividing the length of the reception sequence by the processing length W is W ₀ , the processing number n Is a constant equal to or greater than 1, learning is performed by processing in the reverse direction between symbols “W ₀ + nW + L” to “W ₀ + nW” of the received sequence, and thereafter “W ₀ + nW” to “W ₀ + (n-1) "stores a first resultant value by reverse processing the symbol until, after the above _{operation," W W 0 + (n} -1) symbol W _"from" + L to W 0 + nW " in calculates the second result value by forward processing, the first result value stored the second result value from _{"W 0 + (n-1} ) W""W 0 + nW" until being calculated Using decoding And determines the bit.

Since the conventional turbo code error correction decoding method is as described above, the block length W ₀ of the first stage differs from the block lengths of the other stages according to the code length N which is the length of the reception sequence. Therefore, it is necessary to calculate the block length of the first stage, and when calculating the start position of the constant learning length L when calculating the path metric in the reverse direction, the value changes depending on the code length N Therefore, there has been a problem that the start position of the reverse path metric calculation cannot be easily determined.

  The present invention has been made in order to solve the above-described problems. A turbo code error correction decoding method and a turbo code error correction decoding apparatus capable of easily determining the start position of the reverse path metric calculation. The purpose is to obtain.

  An error correction decoding method for a turbo code according to the present invention includes an information bit sequence, a check bit sequence 1 corresponding to a non-interleaved encoder, and a check corresponding to an interleaved encoder, from a received sequence of a turbo code having a code length N Divided into bit series 2, each separated series is divided into a plurality of blocks, and a reverse path metric and a forward path metric are calculated for each divided block to perform soft input / soft output decoding processing. In each of the separated sequences, a selection is made for each M symbols from the top to constitute one block and divided into K blocks, and the block length from block 1 to block (K-1) is configured to be M symbols. The block length of the last block K is configured as (N−M (K−1)) symbols.

  According to the present invention, when soft input / soft output processing is performed on each of the divided blocks, it is possible to easily determine the start position of the reverse path metric calculation regardless of the code length N. It is done.

FIG. 1 is a block diagram showing a configuration of a turbo code error correction decoding apparatus according to Embodiment 1 of the present invention;
FIG. 2 is a diagram for explaining a received sequence dividing method in the turbo code error correction decoding apparatus according to Embodiment 1 of the present invention;
FIG. 3 is a flowchart showing a turbo code decoding procedure of the turbo code error correction decoding apparatus according to Embodiment 1 of the present invention;
FIG. 4 is a diagram for explaining the timing of path metric calculation in turbo decoding of the turbo code error correction decoding apparatus according to Embodiment 1 of the present invention;
FIG. 5 is a flowchart showing a soft input / soft output decoding procedure corresponding to an encoder without interleaving in the turbo code error correction decoding apparatus according to Embodiment 1 of the present invention;
FIG. 6 is a flowchart showing a soft input / soft output decoding procedure corresponding to an interleaved encoder in the turbo code error correction decoding apparatus according to Embodiment 1 of the present invention;
FIG. 7 is a flowchart showing a turbo code decoding procedure of a turbo code error correction decoding apparatus according to Embodiment 2 of the present invention;
FIG. 8 is a diagram for explaining the timing of path metric calculation in turbo decoding of a turbo code error correction decoding apparatus according to Embodiment 3 of the present invention;
FIG. 9 is a diagram showing addresses of reverse path metric storage means for storing reverse path metrics calculated by reverse path metric calculation means in the turbo code error correction decoding apparatus according to Embodiment 5 of the present invention; .
FIG. 10 is a diagram showing addresses of reverse path metric storage means for storing reverse path metrics calculated by reverse path metric calculation means in the turbo code error correction decoding apparatus according to Embodiment 5 of the present invention; .
FIG. 11 is a diagram showing an address of a reverse path metric storage means for storing a reverse path metric calculated by a reverse path metric calculation means in the turbo code error correction decoding apparatus according to Embodiment 5 of the present invention; .
FIG. 12 is a block diagram showing a configuration of a turbo code error correction decoding apparatus according to Embodiment 6 of the present invention.

Hereinafter, in order to describe the present invention in more detail, the best mode for carrying out the present invention will be described with reference to the accompanying drawings.
Embodiment 1 FIG.
FIG. 1 is a block diagram showing the configuration of a turbo code error correction decoding apparatus according to Embodiment 1 of the present invention. This turbo code error correction decoding apparatus includes received data storage means 1, external information storage means 2, reverse branch metric calculation means 3, reverse path metric calculation means 4, reverse path metric storage means 5, forward branch metric. A calculation unit 6, a forward path metric calculation unit 7, and an LLR (Long Likelihood Ratio) calculation unit 8 are provided.

  The reception data storage unit 1 stores the information bit sequence, the check bit sequence 1 and the check bit sequence 2 separated from the reception sequence 101, and the external information storage unit 2 stores the external information sequence calculated by the LLR calculation unit 8.

  The reverse branch metric calculation means 3 calculates the reverse branch metric, the reverse path metric calculation means 4 calculates the reverse path metric, and the reverse path metric storage means 5 calculates the calculated reverse path metric. Remember.

  The forward branch metric calculation means 6 calculates the forward branch metric, the forward path metric calculation means 7 calculates the forward path metric, and the LLR calculation means 8 is calculated by the forward branch metric calculation means 6. In order to perform the next decoding based on the forward branch metric, the forward path metric calculated by the forward path metric calculation means 7, and the reverse path metric stored in the backward path metric storage means 5. The external information sequence is calculated and updated, and a hard decision decoding sequence is generated and output as a decoding result 102.

Next, the operation will be described.
A reception sequence 101 from a demodulator (not shown) installed in the preceding stage of the turbo code error correction decoding apparatus corresponds to the encoded data from the encoding side, the information bit sequence, the check bit sequence 1 and The check bit series 2 is separated into three series and stored in the received data storage means 1. Here, check bit sequence 1 is a check bit sequence corresponding to a non-interleaved encoder, and check bit sequence 2 is a check bit sequence corresponding to an interleaved encoder.

  FIG. 2 is a diagram for explaining a method of dividing a received sequence. Assuming that the information bit sequence, the check bit sequence 1 and the check bit sequence 2 stored in the received data storage means 1 have a code length N, a block length M, and a number K of divided blocks, K = <N / Divided into M> and read to the backward branch metric calculating means 3 and the forward branch metric calculating means 6. Here, “<>” is a function that rounds up the decimal point when it cannot be divided.

  That is, as shown in FIG. 2, when reading the information bit sequence from the reception data storage means 1 in the order of reception bit sequence and interleaving, or when reading the check bit sequence 1 and the check bit sequence 2, Each block is selected to form one block, which is divided into K blocks, and the block length from block 1 [Block # 1] to block (K-1) [Block # (K-1)] is M symbols. The block length of the last block K [Block # K] is set to the remaining (NM (K-1)) symbols.

  Further, in FIG. 2, the external information sequence stored in the external information storage means 2 is not shown, but as with the information bit sequence, check bit sequence 1 and check bit sequence 2, it is selected every M symbols from the head. To form one block and divide it into K blocks. The block length from block 1 [Block # 1] to block (K-1) [Block # (K-1)] is configured to be M symbols. The block length of the last block K [Block # K] is set to the remaining (NM (K-1)) symbols.

  Soft input / soft output processing is performed on each of the divided blocks as described below. The soft input / soft output calculation method is performed using a logMAP algorithm or a MaxlogMAP algorithm.

  FIG. 3 is a flowchart showing a turbo code decoding procedure. In step ST11, the decoding repetition count j = 1 is set. In step ST12, the information bit sequence read out in the order of the received bit sequence stored in the received data storage unit 1 and the received data storage unit 1 are stored. Based on the check bit sequence 1 and the external information sequence stored in the external information storage unit 2 (however, the values of the external information sequence are all 0 in the first decoding) 3 , A reverse path metric calculation unit 4, a reverse path metric storage unit 5, a forward branch metric calculation unit 6, a forward path metric calculation unit 7 and an LLR calculation unit 8 to be described later, a coding-free interleaved code. The external information sequence is calculated and updated for the next decoding by the soft input soft output decoding procedure corresponding to the device. .

  In step ST13, the updated external information sequence is rearranged in the interleave order and stored in the external information storage means 2.

  In step ST14, the information bit sequence read in the order of interleaving stored in the reception data storage means 1, the check bit sequence 2 stored in the reception data storage means 1, and the external information storage means 2 are stored. Based on the updated external information sequence in the interleave order, reverse branch metric calculation means 3, reverse path metric calculation means 4, reverse path metric storage means 5, forward branch metric calculation means 6, forward path metric According to the soft input / soft output decoding procedure corresponding to the encoding-side interleaved encoder described later performed by the calculating means 7 and the LLR calculating means 8, the external information series is calculated and updated for the next decoding. A hard-decision decoding sequence is generated.

  In step ST15, the external information sequence updated in step ST14 is deinterleaved and rearranged in the order of the received bit sequence and stored in the external information storage means 2.

  In step ST16, it is confirmed whether or not the decoding repetition count j has reached a predetermined decoding repetition count P. If not, the decoding repetition count j is updated in step ST17, and the above steps ST12 to ST15 are performed. repeat.

  When the decoding repetition count j reaches a predetermined decoding repetition count P, the hard decision decoding sequence in the last decoding is output as the decoding result 102 in step ST18.

  FIG. 4 is a diagram for explaining the timing of path metric calculation in turbo decoding. Here, the reverse path metric calculation timing from block 1 [Block # 1] to block K [Block #K] by the reverse path metric calculation means 4 and the block 1 [Block # by the forward path metric calculation means 7 are described. The timing of forward path metric calculation from # 1] to block K [Block # K] and the calculation of the external information series from block 1 [Block # 1] to block K [Block # K] by the LLR calculation means 8 And the output timing of the decoding result 102 is shown.

  In the reverse path metric calculation of FIG. 4, the L symbol 201 added before block 1 [Block # 1] is the first L symbol in the M symbols of the subsequent block 2 [Block # 2]. Before calculating the path metric in the reverse direction of the M symbols in block 1, in order to calculate the initial value of the path metric in the reverse direction, the first L symbols for the M symbols in the next block 2 are used as the number of margin symbols. It shows the use of reverse path metric calculation learning. That is, the path metric in the reverse direction of block 1 is calculated from the Lth symbol of block 2.

  Similarly, L symbols 202, 203, 208, and 209 added in front of each block are the head L symbols in the M symbols of the subsequent blocks, and the path metric in the reverse direction of the M symbols of each block. Before the calculation, learning of path metric calculation in the reverse direction is performed using the first L symbols in the M symbols of each subsequent block as the number of margin symbols. However, since there is no subsequent block for the last block K [Block # K], learning using the L symbol 209 is not actually performed.

  In the reverse path metric calculation of FIG. 4, the reverse path metric calculation means 4 calculates the reverse path metric of block 1 from the L-th symbol of block 2, and the calculated reverse path metric is the reverse path. The data is stored in the metric storage unit 5. Next, the reverse path metric calculation means 4 calculates the reverse path metric of the block 2 from the Lth symbol of the block 3 and stores it in the reverse path metric storage means 5, and at the same time the forward path metric calculation means 7 The forward path metric of block 1 is calculated, and then the LLR calculation means 8 calculates an external information sequence for the reverse path metric and the forward path metric of block 1, and stores the calculated external information sequence as external information. The data is stored in the means 2. The reverse block metric calculation means 4 calculates the reverse path metric of the block K and stores it in the reverse path metric storage means 5 at the same time as the forward path metric calculation means 7. Calculates a forward path metric of the block (K-1), and then calculates an external information sequence for the reverse path metric and the forward path metric of the block (K-1). Is stored in the external information storage means 2. Finally, the forward path metric calculation means 7 calculates the forward path metric of the block K, and then the LLR calculation means 8 calculates the external information series for the reverse path metric and the forward path metric of the block K. Then, the calculated external information series is stored in the external information storage means 2.

  FIG. 5 is a flowchart showing the soft input / soft output decoding procedure corresponding to the encoder without interleaving in step ST12 of FIG. In step ST21, the information bit sequence stored in the reception data storage unit 1 is divided into K blocks in the order of reception and read out, and the check bit sequence 1 stored in the reception data storage unit 1 is K pieces. The external information series (divided into blocks and read out) and stored in the external information storage means 2 (however, the values of the external information series are all 0 at the time of the first decoding) are each divided into K blocks. And read.

  In step ST22, after the backward branch metric calculating unit 3 calculates the backward branch metric, the backward path metric calculating unit 4 converts the backward path metric of the block 1 [Block # 1] into the block 2 [Block # 2]. ], The reverse path metric of block 1 among the calculated reverse path metrics is stored in the reverse path metric storage means 5.

  In step ST23, the block number variable i is set to 1. In step ST24, it is checked whether the block number variable i is the last block K. The block number variable i must be the last block K. If so, the process proceeds to step ST25.

  In step ST25, the reverse path metric calculation means 4 calculates the reverse path metric of the block 2 [Block # 2] from the L (<M) th symbol of the block 3 [Block # 3], and calculates the reverse direction metric. Of the path metrics, the reverse path metric of block 2 is stored in the reverse path metric storage means 5. At the same time, after the forward branch metric calculating unit 6 calculates the forward branch metric, the forward path metric calculating unit 7 calculates the forward path metric of the block 1. Then, the LLR calculation unit 8 includes the reverse path metric of the block 1 stored in the reverse path metric storage unit 5 and the forward branch metric of the block 1 calculated by the forward branch metric calculation unit 6. Based on the forward path metric of block 1 calculated by forward path metric calculation means 7, the external information sequence of block 1 is calculated and the external information series is stored in external information storage means 2 and the hard decision value is calculated. To do.

  In step ST26, the variable i of the block number is updated, and the processes in steps ST24 and ST25 are repeated. Similarly, the path metric calculation in the reverse direction of the block (i + 1) [Block # (i + 1)] and the block i [Block # i] is simultaneously performed using the updated external information series, and the LLR calculation means 8 performs the reverse path metric of the block i stored in the reverse path metric storage means 5. An external information sequence of block i based on the forward branch metric of block i calculated by forward branch metric calculation means 6 and the forward path metric of block i calculated by forward path metric calculation means 7. Calculate and update and store in the external information storage means 2 and calculate the hard decision value .

  When the block number variable i becomes the last block K in step ST24, in step ST27, the forward path metric calculation means 7 uses the updated external information sequence to forward the block K forward path metric. Calculate Then, the LLR calculation means 8 has the reverse path metric of the block K stored in the reverse path metric storage means 5, the forward branch metric of the block K calculated by the forward branch metric calculation means 6, Based on the forward path metric of the block K calculated by the forward path metric calculation means 7, the external information sequence of the block K is calculated and updated and stored in the external information storage means 2 and the hard decision value is calculated.

  FIG. 6 is a flowchart showing a soft input / soft output decoding procedure corresponding to an interleaved encoder in step ST14 of FIG. In step ST31, the information bit sequence stored in the reception data storage means 1 is divided into K blocks and read out in an interleaved order, and the check bit sequence 2 stored in the reception data storage means 1 is K pieces. External information sequences read out after being divided into blocks and rearranged in the interleaving order stored in the external information storage means 2 (however, the values of the external information sequences are all 0 at the time of the first decoding). The data is divided into K blocks and read.

  In step ST32, after the backward branch metric calculating unit 3 calculates the backward branch metric, the backward path metric calculating unit 4 converts the backward path metric of the block 1 [Block # 1] into the block 2 [Block # 2]. ], The reverse path metric of block 1 among the calculated reverse path metrics is stored in the reverse path metric storage means 5.

  In step ST33, the block number variable i is set to 1. In step ST34, it is checked whether the block number variable i is the last block K. The block number variable i must be the last block K. If so, the process proceeds to step ST35.

  In step ST35, the reverse path metric calculation means 4 calculates the reverse path metric of the block 2 [Block # 2] from the L (<M) th symbol of the block 3 [Block # 3], and the calculated reverse path. Of the metrics, the reverse path metric of block 2 is stored in the reverse path metric storage means 5. At the same time, after the forward branch metric calculating unit 6 calculates the forward branch metric of the block 1, the forward path metric calculating unit 7 calculates the forward path metric of the block 1. Then, the LLR calculation unit 8 includes the reverse path metric of the block 1 stored in the reverse path metric storage unit 5 and the forward branch metric of the block 1 calculated by the forward branch metric calculation unit 6. Based on the forward path metric of the block 1 calculated by the forward branch metric calculation means 6, the external information series of the block 1 is calculated and stored in the external information storage means 2, and the hard decision value is calculated.

  In step ST36, the variable i of the block number is updated, and the processes in steps ST34 and ST35 are repeated, and the path metric calculation in the reverse direction of the block (i + 1) [Block # (i + 1)] and the block i [Block # i] is simultaneously performed using the updated external information series, and the LLR calculation means 8 performs the reverse path metric of the block i stored in the reverse path metric storage means 5. And the forward branch metric of the block i calculated by the forward branch metric calculation means 6 and the forward path metric of the block i calculated by the forward path metric calculation means 7, Is calculated and updated and stored in the external information storage means 2 and the hard decision value is calculated. That.

  When the block number variable i becomes the last block K in step ST34, the forward path metric calculation means 7 uses the updated external information sequence in step ST37 to forward the block K in the forward direction. Calculate the metric. Then, the LLR calculation means 8 has the reverse path metric of the block K stored in the reverse path metric storage means 5, the forward branch metric of the block K calculated by the forward branch metric calculation means 6, Based on the forward path metric of the block K calculated by the forward path metric calculating means 7, the external information sequence of the block K is calculated and the hard decision value is calculated.

  As described above, according to the first embodiment, for the information bit sequence, check bit sequence 1, check bit sequence 2, and external information sequence, one block is configured for each M symbols from the head of the code length N symbols. Are divided into K blocks, with block 1 to block (K-1) being M symbols and the last block K being the remaining (NM (K-1)) symbols. In addition, when the soft input / soft output process is performed on each block, an effect is obtained in which the start position of the path metric calculation in the reverse direction can be easily determined regardless of the code length N.

Embodiment 2. FIG.
The block diagram showing the configuration of the turbo code error correction decoding apparatus according to the second embodiment of the present invention is the same as FIG. 1 of the first embodiment. The received sequence dividing method of the second embodiment is the same as that of FIG. 2 of the first embodiment, and the timing of path metric calculation of the second embodiment is the same as that of FIG. 4 of the first embodiment. The same. In the first embodiment, the LLR calculation unit 8 outputs the hard decision decoding sequence as the decoding result 102 in the order of interleaving of the information bit sequence. In the second embodiment, the LLR calculation unit 8 receives the information bit sequence. The hard decision decoding sequence is output as the decoding result 102 in the bit sequence order, that is, in the order of the head of the information bit sequence.

Next, the operation will be described.
FIG. 7 is a flowchart showing a turbo code decoding procedure of the turbo code error correction decoding apparatus according to the second embodiment of the present invention. The flowchart shown in FIG. 7 is basically the same as that obtained by replacing the processes of steps ST12 and ST13 of FIG. 3 of the first embodiment with the processes of steps ST14 and ST15.

  That is, the process in step ST42 in FIG. 7 is basically the same as the process in step ST14 in FIG. 3, and the hard decision decoding sequence generation process performed in step ST14 in FIG. This step ST42 is not performed. Further, the process in step ST43 in FIG. 7 is the same as the process in step ST15 in FIG. 3, the process in step ST44 in FIG. 7 is basically the same as the process in step ST12 in FIG. The hard decision decoding sequence generation process not performed in step ST12 of FIG. 3 is performed in step ST44 of FIG. Further, the processing in step ST45 in FIG. 7 is the same as the processing in step ST13 in FIG. 3, and the processing in other steps ST41, ST46, ST47, and ST48 in FIG. 7 is performed in steps ST11 and ST16 in FIG. , ST17 and ST18 are the same.

  In this way, first, the external information sequence is updated by combining the interleaved order information bit sequence, the check bit sequence 2, and the interleaved order external information sequence, and then the interleaved updated external information sequence is deinterleaved. Then, rearrangement is performed in the order of the received bit sequence, and the external information sequence is calculated by combining the information bit sequence in the order of the received bit sequence, the check bit sequence 1, and the external information sequence. By performing the decoding process by repeating this operation, the LLR calculation unit 8 outputs the hard decision decoding sequence as the decoding result 102 in the order of the received bit sequence of the information bit sequence, that is, the head of the information bit sequence.

  In the case where an error detection code such as CRC (Cyclic Redundancy Check) is added to the information bit sequence, in the first embodiment, the hard decision decoding sequence is output as the decoding result 102 in the order of interleaving of the information bit sequence. Therefore, it is necessary to store CRC results 102 in a memory (not shown) and rearrange them in the order of received bit sequences, and then perform a CRC operation. By outputting as the decoding result 102, it is not necessary to store or rearrange in the memory, and error detection operation processing such as CRC can be performed at high speed.

  As described above, according to the second embodiment, as in the first embodiment, the start position of the path metric calculation in the reverse direction can be easily determined regardless of the code length N. It is done.

  According to the second embodiment, the external information sequence is first updated by combining the information bit sequence in the interleave order, the check bit sequence 2, and the external information sequence in the interleave order. Then, the updated external information sequence is updated. The information sequence is deinterleaved and rearranged in the order of the received bit sequence, and the decoding result 102 is calculated by combining the information bit sequence in the order of the received bit sequence, the check bit sequence 1, and the external information sequence. Are output in the order of the beginning of the information bit sequence, and an error detection operation process such as CRC can be performed at high speed.

Embodiment 3 FIG.
The block diagram showing the configuration of the turbo code error correction decoding apparatus according to the third embodiment of the present invention is the same as FIG. 1 of the first embodiment. Further, the method of dividing the received sequence in the third embodiment is the same as that in FIG. 2 of the first embodiment. In this third embodiment, when tail bits are inserted at the block end of the reception sequence 101 so that the internal state at the block end becomes a fixed value (usually 0), the path metric is calculated in the reverse direction. Is performed using the tail bit.

Next, the operation will be described.
The flowchart showing the decoding procedure of the turbo code in the third embodiment is the same as the process shown in FIG. 3 of the first embodiment, and the soft input soft corresponding to the encoder without interleaving in the third embodiment. A flowchart showing an output decoding procedure and a flowchart showing a soft input / soft output decoding procedure corresponding to an interleaved encoder are the same as those in FIGS. 5 and 6 of the first embodiment, respectively.

  FIG. 8 is a diagram for explaining the timing of path metric calculation in the turbo decoding according to the third embodiment. Compared with FIG. 4 in the first embodiment, the block (K− The difference is that the L symbol 208 added before 1) becomes the Lx symbol 218, and the L symbol 209 added before block K becomes the tail bit (Tail) 219.

  Here, the flowchart showing the decoding procedure is the same as that described in the first embodiment, and the operation of the portion different from the portion described in the first embodiment will be described with reference to FIG.

  In the process of calculating the external information series, in the first embodiment, when the backward path metric calculating means 4 calculates the backward path metric, the value of the number L of margin symbols for learning as a margin is predetermined. When the path metric calculation in the reverse direction is performed, the block length (N−M (K−1)) symbol of the final block K with respect to the information bit sequence stored in the reception data storage unit 1 Is short, the L symbol 208 of the block (K-1) in FIG. 4 cannot take a predetermined fixed value, and the path metric calculation in the reverse direction of the block (K-1) is performed.

  On the other hand, in the third embodiment, when the reverse path metric calculation means 4 calculates the reverse path metric, as shown in FIG. From 1 [Block # 1] to block (K-2) [Block # (K-2)] (not shown), the value of the margin symbol number L is a predetermined fixed value, and the block ( K-1) For [Block # (K-1)], the value of the margin symbol number Lx is Lx = Min (L, NM (K-1)), that is, the value of the margin symbol number L. Alternatively, the smaller block length (NM (K-1)) of block K [Block # K] is taken. When LX = L, the initial value of the path metric in the reverse direction is calculated from the same value L in each state. When Lx = N−M (K−1), the value of state 0 is calculated. After calculating the tail bit path metric, the path metric is calculated in the reverse direction from the Lx symbol of the block K [Block # K]. For block K, the value of state 0 is increased as the initial value of the reverse path metric, the tail bit path metric is calculated, and then the reverse path metric of block K is calculated to obtain the tail bit. Information can be effectively used, the reverse path metric can be calculated efficiently at high speed, and the learning period can be secured in the reverse path metric calculation of the block (K-1) and the block K. The performance can be improved.

  As described above, according to the third embodiment, as in the first embodiment, the start position of the path metric calculation in the reverse direction can be easily determined regardless of the code length N. It is done.

  Further, according to the third embodiment, when a tail bit is inserted at the end of the block of the received sequence, the tail bit information is made effective by calculating the reverse path metric using the tail bit. The reverse path metric can be calculated efficiently at high speed, and the performance can be improved in the entire decoding operation.

  Note that the same effect can be obtained in the third embodiment even if decoding is performed in the decoding procedure of the second embodiment.

Embodiment 4 FIG.
The block diagram showing the configuration of the turbo code error correction decoding apparatus according to the fourth embodiment of the present invention is the same as FIG. 1 of the first embodiment. Also, the received sequence dividing method, the turbo code decoding procedure, the path metric calculation timing, the soft input soft output decoding procedure corresponding to the encoder without interleaving, and the encoder without interleaving according to the fourth embodiment. Corresponding soft input / soft output decoding procedures are the same as those in FIGS. 2, 3, 4, 5, and 6 of the first embodiment.

Next, the operation will be described.
In step ST25 of FIG. 5 and step ST35 of FIG. 6, when the forward path metric calculation means 7 calculates the forward path metric, i (i = 1, 2,..., (K−1) )) The initial value when calculating the forward path metric of the next (i + 1) th block by temporarily saving the forward path metric of the final point of the first block to a memory (not shown) or the like. And For example, the forward path metric at the end of block 1 in the forward path metric calculation of FIG. 4 is temporarily saved in the memory and used as the initial value when the forward path metric of the next block 2 is calculated. . In this way, by temporarily saving the forward path metric of the last time of the i-th block in the memory and setting the initial value when calculating the forward path metric of the next (i + 1) -th block, The accuracy of the forward path metric is improved, and the performance can be improved in the entire decoding operation.

  As described above, according to the fourth embodiment, as in the first embodiment, the start position of the path metric calculation in the reverse direction can be easily determined regardless of the code length N. It is done.

  Further, according to the fourth embodiment, when the forward path metric calculating means 7 calculates the forward path metric, the forward path metric at the final time point of each block is temporarily saved, and the following is performed. By using the initial value when calculating the forward path metric of the block, the accuracy of the forward path metric is improved, and the performance can be improved in the entire decoding operation.

  Note that the same effect can be obtained for the fourth embodiment even if decoding is performed in the decoding procedure of the second embodiment.

Embodiment 5 FIG.
The block diagram showing the configuration of the turbo code error correction decoding apparatus according to the fifth embodiment of the present invention is the same as FIG. 1 of the first embodiment. In addition, the received sequence dividing method, the turbo code decoding procedure, the path metric calculation timing, the soft input soft output decoding procedure corresponding to the encoder without interleaving, and the encoder without interleaving according to the fifth embodiment. Corresponding soft input / soft output decoding procedures are the same as those in FIGS. 2, 3, 4, 5, and 6 of the first embodiment.

Next, the operation will be described.
When the backward path metric value calculated by the backward path metric calculating means 4 is stored in the backward path metric storage means 5, the memory capacity of M words is stored as the backward path metric storage means 5. Is required. When the backward path metric calculation means 4 calculates the backward path metric value of the next block, the LLR calculation means 8 reads the backward path metric stored in the backward path metric storage means 5 at the same time. It is necessary to store the calculated backward path metric of the next block in the backward path metric storage means 5. Therefore, in the first embodiment, the reverse path metric storage means 5 requires a memory capacity of 2 M words in total, that is, a write area M words and a read area M words.

  FIG. 9 is a diagram showing the address of the reverse path metric storage means 5 for storing the reverse path metric calculated by the reverse path metric calculation means 4 in FIG. FIG. 9A shows a write address when writing a path metric in the reverse direction of block 1 [Block # 1]. FIG. 9B shows a read address and a block i [Block when reading the path metric in the reverse direction of the block (i−1) [Block # (i−1)] when the variable i of the block number is an even number. The write address for writing the path metric in the reverse direction of #i] is shown. Further, FIG. 9 (c) shows the read address and the block i [Block] when reading the reverse path metric of the block (i-1) [Block # (i-1)] when the variable i of the block number is an odd number. The write address for writing the path metric in the reverse direction of #i] is shown.

  FIG. 10 is a diagram showing the address of the reverse path metric storage means 5 for storing the reverse path metric calculated by the reverse path metric calculation means 4 in FIG. FIG. 10 (a) shows the read address and block K [Block # K when reading the path metric in the reverse direction of the block (K-1) [Block # (K-1)] when the final block number K is an even number. ] Shows the write address when writing the path metric in the reverse direction. FIG. 10B shows the read address when reading the path metric in the reverse direction of the block K [Block # K] when the final block number K is an even number.

  FIG. 11 is a diagram showing the address of the reverse path metric storage means 5 for storing the reverse path metric calculated by the reverse path metric calculation means 4 in FIG. FIG. 11A shows a read address and a block K [Block # K when reading the reverse path metric of the block (K-1) [Block # (K-1)] when the final block number K is an odd number. ] Shows the write address when writing the path metric in the reverse direction. FIG. 11B shows the read address when reading the path metric in the reverse direction of the block K [Block # K] when the last block number K is an odd number.

  First, when the reverse path metric calculation means 4 performs the reverse path metric calculation of the block 1, the reverse path metric storage means stores the reverse path metric of the block 1 as shown in FIG. 9 (a). 5 are written in ascending order from address 0 to address (M−1).

  Next, when the reverse path metric calculation means 4 simultaneously performs the reverse path metric calculation of the block 2 (i is an even number) and the forward path metric calculation means 7 simultaneously perform the forward path metric calculation of the block 1, As shown in FIG. 9 (b), the LLR calculation means 8 reads the reverse path metric of the block 1 from the address (M-1) of the reverse path metric storage means 5 to the address 0 in descending order. At the same time, the reverse path metric calculation unit 4 writes the reverse path metric of the block 2 in the reverse path metric storage unit 5, but after the LLR calculation unit 8 reads the reverse path metric value of the block 1 The addresses are written in descending order from the address (M-1) of the reverse path metric storage means 5 to the address 0. At this time, the timing difference between reading the path metric in the reverse direction of the block 1 and writing the path metric in the reverse direction of the block 2 is the learning period of the path metric calculation in the reverse direction of the block 2.

  Next, when the reverse path metric calculation of the block 3 (i is an odd number) by the reverse path metric calculation means 4 and the forward path metric calculation of the block 2 by the forward path metric calculation means 7 are performed simultaneously, As shown in FIG. 9 (c), the LLR calculation means 8 reads the backward path metric of the block 2 in ascending order from the address 0 to the address (M-1) of the backward path metric storage means 5. At the same time, the reverse path metric calculation means 4 writes the reverse path metric of the block 3 in the reverse path metric storage means 5, but after the LLR calculation means 8 reads the reverse path metric of the block 2, Data is written in ascending order from address 0 to address (M−1) in the backward path metric storage means 5. At this time, the timing difference between reading the path metric in the reverse direction of the block 2 and writing the path metric in the reverse direction of the block 3 is the learning period of the path metric calculation in the reverse direction of the block 3.

  Similarly, for block 4 and subsequent blocks, as shown in FIG. 9 (b) and FIG. 9 (c), when writing the path metric in the reverse direction depending on the even or odd block number of the block to be processed. The memory capacity of the backward path metric storage unit 5 can be reduced to M words by generating the reverse path metric storage unit 5 by replacing the addresses of the backward path metric storage unit 5 in descending or ascending order.

  Next, when the reverse path metric calculation of the block K of the final block number K and the path metric calculation of the block (K-1) forward direction are performed, depending on whether the final block number K is even or odd, FIG. And the address of the backward path metric storage means 5 is generated as shown in FIG.

  When the block number K is an even number, as shown in FIG. 10 (a), the LLR calculation means 8 converts the reverse path metric of the block (K-1) to the address (M of the reverse path metric storage means 5). Read from -1) to address 0 in descending order. At the same time, the reverse path metric calculation means 4 stores the reverse path metric of the block K in the reverse path metric storage means 5, while the LLR calculation means 8 stores the reverse path metric of the block (K-1). After the metrics are read out, they are written in descending order from address (M-1) to address (MK-N). At this time, the timing difference between the reverse path metric reading of the block (K-1) and the reverse path metric writing of the block K is the learning period of the reverse path metric calculation of the block K. Finally, when the forward path metric calculation of the block K by the forward path metric calculation means 7 is performed, the LLR calculation means 8 calculates the reverse path metric of the block K as shown in FIG. Reading is performed in ascending order from the address (MK-N) to the address (M-1) of the backward path metric storage unit 5.

  When the block number K is an odd number, as shown in FIG. 11 (a), the LLR calculation means 8 changes the backward path metric of the block (K-1) from the address 0 of the backward path metric storage means 5. Reading is performed in ascending order until address (M-1). At the same time, the reverse path metric calculation means 4 stores the reverse path metric of the block K in the reverse path metric storage means 5, while the LLR calculation means 8 stores the reverse path metric of the block (K-1). After the metrics are read out, they are written in ascending order from address 0 to address (NM (K-1) -1). At this time, the timing difference between the reverse path metric reading of the block (K-1) and the reverse path metric writing of the block K is the learning period of the reverse path metric calculation of the block K. Finally, when the forward path metric calculation of the block K by the forward path metric calculation means 7 is performed, the LLR calculation means 8 calculates the reverse path metric of the block K as shown in FIG. Reading is performed in descending order from the address (NM (K-1) -1) of the backward path metric storage means 5 to the address 0.

  The addresses shown in FIGS. 9, 10 and 11 can be generated by address generating means (not shown) connected to the reverse path metric storage means 5 of FIG.

  As described above, according to the fifth embodiment, similarly to the first embodiment, an effect is obtained in which the start position of the reverse path metric calculation can be easily determined regardless of the code length N. It is done.

  Further, according to the fifth embodiment, the addresses of the backward path metric storage means 5 when the backward path metric is written are switched in descending or ascending order according to the even or odd block number of the block to be processed. By generating, the memory capacity of the backward path metric storage means 5 can be suppressed to M words, and the memory capacity of the backward path metric storage means 5 can be reduced.

  Note that the same effect can be obtained in the fifth embodiment even if decoding is performed in the decoding procedure of the second embodiment.

Embodiment 6 FIG.
FIG. 12 is a block diagram showing the configuration of a turbo code error correction decoding apparatus according to Embodiment 6 of the present invention. This turbo code error correction decoding apparatus has the configuration shown in FIG. 1 of the first embodiment, with a reverse read address generation means 31, a forward read address generation means 32, a reverse read address generation means 33, a forward direction. A read address generation unit 34, an external information write address generation unit 35, a switching unit 36, a switching unit 37, a write address generation unit 38, a read address generation unit 39, and a control unit 40 are added.

  The received data storage means 1 includes an information bit sequence storage means 11, a check bit sequence 1 storage means 12, and a check bit sequence 2 storage means 13. Information storage means 21 and interleaved order external information storage means 22 are provided.

  The information bit sequence storage means 11 stores the information bit sequence separated from the reception sequence 101 (not shown), and the check bit sequence 1 storage means 12 stores the check bit sequence 1 separated from the reception sequence 101. Bit sequence 2 storage means 13 stores check bit sequence 2 separated from reception sequence 101. The reception bit sequence order external information storage unit 21 stores the external information sequence from the LLR calculation unit 8 in the order of reception bit sequence, and the interleave order external information storage unit 22 stores the external information sequence from the LLR calculation unit 8 in the interleaving order.

  The reverse direction read address generation unit 31 generates read addresses of the information bit sequence storage unit 11, the reception bit sequence order external information storage unit 21, and the interleaved order external information storage unit 22 for reverse path metric calculation. The direction read address generation unit 32 generates read addresses of the information bit sequence storage unit 11, the reception bit sequence order external information storage unit 21, and the interleaved order external information storage unit 22 for forward path metric calculation.

  The reverse direction read address generation means 33 generates the read address of the check bit sequence 1 storage means 12 and the check bit sequence 2 storage means 13 for the reverse path metric calculation, and the forward read address generation means 34 Read addresses of the check bit sequence 1 storage unit 12 and the check bit sequence 2 storage unit 13 for path metric calculation are generated.

  The external information write address generation means 35 generates a write address for writing the external information series from the LLR calculation means 8 in the received bit sequence order external information storage means 21 and the interleave order external information storage means 22.

  The switching means 36 selects the output from the check bit series 1 storage means 12 or the check bit series 2 storage means 13, and the switching means 37 outputs from the received bit series order external information storage means 21 or the interleave order external information storage means 22. Select.

  The write address generation means 38 generates a write address for writing the reverse path metric to the reverse path metric storage means 5, and the read address generation means 39 stores the reverse direction metric stored in the reverse path metric storage means 5. A read address for reading the path metric is generated.

  The control means 40 pre-calculates and holds the code length N, the number of blocks K, the block length M, and the number of margin bits L, and provides control for performing each process by giving the held numerical values to each means. Generate a signal.

  Other reverse branch metric calculation means 3, reverse path metric calculation means 4, reverse path metric storage means 5, forward branch metric calculation means 6, forward path metric calculation means 7 and LLR calculation means 8 are the embodiments. Same as 1.

Next, the operation will be described.
The received sequence dividing method, turbo code decoding procedure, path metric calculation timing, soft input / soft output decoding procedure corresponding to an uninterleaved encoder, and an interleaved encoder according to the sixth embodiment. The soft input / soft output decoding procedure is basically the same as that of the first embodiment shown in FIG. 2, FIG. 3, FIG. 4, FIG. 5 and FIG. The generation of the read address and the write address of the means 11, the check bit sequence 1 storage means 12, the check bit sequence 2 storage means 13, the received bit sequence order external information storage means 21 and the interleave order external information storage means 22 will be described in detail.

  Received sequence 101 demodulated by a demodulator (not shown) is separated into information bit sequence, check bit sequence 1 and check bit sequence 2 as soft decision information, and information bit sequence storage means 11, check bit sequence, respectively. 1 storage means 12 and check bit sequence 2 storage means 13.

First, a decoding operation corresponding to an encoder without interleaving is performed.
First, the following operation is performed on block 1 with block number variable i = 1.

  The addresses of the reverse direction read address generation means 31 and the reverse direction read address address generation means 33 are set to (M + L−1). This address (M + L-1) is the head address of the L symbol 201 in the reverse path metric calculation of FIG. Then, the information bit sequence, the check bit sequence 1 and the external information sequence are read from the information bit sequence storage unit 11, the check bit sequence 1 storage unit 12 and the received bit sequence order external information storage unit 21, respectively. However, at the time of the first decoding, the external information sequence read from the received bit sequence order external information storage means 21 is set to 0. Values read from the check bit sequence 1 storage unit 12 and the received bit sequence order external information storage unit 21 are selected by the switching unit 36 and the switching unit 37, respectively, and input to the backward branch metric calculation unit 3. The reverse branch metric calculation means 3 calculates the reverse branch metric, and the reverse path metric calculation means 4 calculates the reverse path metric.

  The same operation is performed until the values of the reverse direction read address generation means 31 and the reverse direction read address generation means 33 are counted down and the address becomes 0 (the final address of the block 1 in the reverse path metric calculation of FIG. 4). The reverse path metric calculation means 4 calculates the reverse path metric.

  Then, the reverse path metric storage unit 5 stores the reverse path metric values in which the addresses of the reverse direction read address generation unit 31 and the reverse direction read address generation unit 33 are M to 1. At this time, the write address generation unit 38 generates the write address of the backward path metric storage unit 5 by the procedure described in the fifth embodiment, for example.

Next, the following operation is repeated for each block of the block number variable i (i = 2, 3,..., K).
The addresses of the reverse direction read address generation unit 31 and the reverse direction read address generation unit 33 are set to (iM + L−1 (i = 2, 3,..., K)). This address (iM + L-1) is the head address of the L symbols 202, 203,..., 208, 209 in the reverse path metric calculation of FIG. Then, the information bit sequence, the check bit sequence 1 and the external information sequence are read from the information bit sequence storage unit 11, the check bit sequence 1 storage unit 12 and the received bit sequence order external information storage unit 21, respectively. However, at the time of the first decoding, the external information sequence read from the received bit sequence order external information storage means 21 is set to 0.

  At the same time, the addresses of the forward read address generation means 32 and the forward read address generation means 34 are set to (M (i−2)). This address (M (i-2)) is the head address of blocks 1 to K in the forward path metric calculation of FIG. Then, the information bit sequence, the check bit sequence 1 and the external information sequence are read from the information bit sequence storage unit 11, the check bit sequence 1 storage unit 12 and the received bit sequence order external information storage unit 21, respectively. However, at the time of the first decoding, the external information sequence read from the received bit sequence order external information storage means 21 is set to 0.

  The values read from the check bit sequence 1 storage unit 12 and the received bit sequence order external information storage unit 21 at the addresses of the reverse direction read address generation unit 31 and the reverse direction read address generation unit 33 are the switching unit 36 and the switching unit. It is selected at 37 and inputted to the backward branch metric calculation means 3. The reverse branch metric calculation means 3 calculates the reverse branch metric, and the reverse path metric calculation means 4 calculates the reverse path metric.

  The values read from the check bit sequence 1 storage unit 12 and the received bit sequence order external information storage unit 21 at the addresses of the forward read address generation unit 32 and the forward read address generation unit 34 are the switching unit 36 and It is selected by the switching means 37 and input to the forward branch metric calculation means 6. The forward branch metric calculation means 6 calculates a forward branch metric, and the forward path metric calculation means 7 calculates a forward path metric.

  The LLR calculation unit 8 includes the forward branch metric calculated by the forward branch metric calculation unit 6, the forward path metric calculated by the forward path metric calculation unit 7, and the description in the fifth embodiment. The external information series is calculated from the reverse path metric read from the reverse path metric storage means 5 by the address of the read address generation means 39 generated in the procedure. The address of the external information write address generation means 35 is set to (M (i-2)). This address (M (i-2)) is the head address of blocks 1 to K in the external information calculation of FIG. Then, the external information sequence calculated by the LLR calculation means 8 is written into the interleaved order external information storage means 22.

  Thereafter, the addresses of the reverse direction read address generation unit 31 and the reverse direction read address generation unit 33 are counted down to ((M−1) i). This address ((M-1) i) is the final address of blocks 2 to K in the reverse path metric calculation of FIG. Further, the forward read address generation means 32 and the forward read address generation means 34 are counted up to (M (i−1) −1). This address (M (i-1) -1) is the final address of block 1 to block K in the forward path metric calculation of FIG. Further, the address of the external information write address generation means 35 is counted up to (M (i−1) −1), and the external information series is sequentially calculated and written in the interleaved order external information storage means 22. This address (M (i-1) -1) is the final address of block 1 to block K in the external information calculation of FIG.

  For the last block K, the addresses of the forward direction read address generation means 32 and the forward direction read address generation means 34 are set to (M (K-1)). This address (M (K-1)) is the head address of the block K in the forward path metric calculation of FIG. Further, the address of the external information write address generation means 35 is set to (M (K-1)). This address (M (K-1)) is the head address of the block K in the external information calculation of FIG. Then, the information bit sequence, the check bit sequence 1 and the external information sequence are read from the information bit sequence storage unit 11, the check bit sequence 1 storage unit 12 and the received bit sequence order external information storage unit 21, respectively. However, at the time of the first decoding, the external information sequence read from the received bit sequence order external information storage means 21 is set to 0.

  The values read from the test bit sequence 1 storage unit 12 and the received bit sequence order external information storage unit 21 at the addresses of the forward direction read address generation unit 32 and the forward direction read address generation unit 34 are the switching unit 36 and the switching unit. The selection is made at 37 and inputted to the forward branch metric calculation means 6. The forward branch metric calculation means 6 calculates a forward branch metric, and the forward path metric calculation means 7 calculates a forward path metric.

  The LLR calculation unit 8 includes the forward branch metric calculated by the forward branch metric calculation unit 6, the forward path metric calculated by the forward path metric calculation unit 7, and the description in the fifth embodiment. The external information series is calculated from the reverse path metric read from the reverse path metric storage means 5 by the address of the read address generation means 39 generated in the procedure, and the interleaving designated by the external information write address generation means 35 is performed. Write to the address of the sequential external information storage means 22.

  Thereafter, the addresses of the forward read address generation means 32 and the forward read address generation means 34 are counted up to (N−1). This address (N-1) is the final address of the block K in the forward path metric calculation of FIG. Further, the address of the external information write address generation means 35 is counted up to (N-1). This address (N-1) is the final address of the block K in the external information calculation of FIG.

Next, a decoding operation corresponding to an interleaved encoder is performed.
First, the following operation is performed on block 1 with block number variable i = 1.

  The address of the backward read address generation means 31 is set to the (M + L−1) th address in a turbo interleave table (not shown), and the information bit series and the interleave order external information storage means 22 Read external information series. Further, the address of the backward read address generation means 33 is set to (M + L−1), and the check bit series 2 is read from the check bit series 2 storage means 13. The values read from the check bit sequence 2 storage unit 13 and the interleaved order external information storage unit 22 are selected by the switching unit 36 and the switching unit 37 and input to the backward branch metric calculation unit 3. The reverse branch metric calculation means 3 calculates the reverse branch metric, and the reverse path metric calculation means 4 calculates the reverse path metric.

  The address of the backward read address generating means 31 is sequentially set to the previous address in the turbo interleave table, the address of the backward read address generating means 33 is counted down, and the same operation is repeated until the address becomes 0, The reverse path metric calculation means 4 calculates the reverse path metric, and the reverse path metric storage means 5 stores the reverse path metric in which the address of the reverse read address generation means 33 is M to 1. At this time, the write address generation unit 38 generates address 0 from the write address (M−1) of the backward path metric storage unit 5 by the procedure described in the fifth embodiment, for example.

Next, the following operation is repeated for each block of the block number variable i (i = 2, 3,..., K).
The address of the reverse read address generation means 31 is set to the (iM + L−1) th (i = 2, 3,..., K) address in the turbo interleave table, and the address of the reverse read address generation means 33 is ( iM + L-1 (i = 2, 3,..., K)). Then, the information bit sequence, the check bit sequence 2 and the external information sequence are read from the information bit sequence storage unit 11, the check bit sequence 2 storage unit 13 and the interleave order external information storage unit 22, respectively.

  At the same time, the address of the forward direction read address generation means 32 is set to the (M (i−2)) th (i = 2, 3,..., K) address in a turbo interleave table (not shown). The address of the direction read address generation means 34 is set to (M (i-2)). Then, the information bit sequence, the check bit sequence 2 and the external information sequence are read from the information bit sequence storage unit 11, the check bit sequence 2 storage unit 13 and the interleave order external information storage unit 22, respectively.

  The values read from the test bit sequence 2 storage unit 13 and the interleaved order external information storage unit 22 at the addresses of the reverse direction read address generation unit 31 and the reverse direction read address generation unit 33 are changed by the switching unit 36 and the switching unit 37. It is selected and input to the backward branch metric calculation means 3. The reverse branch metric calculation means 3 calculates the reverse branch metric, and the reverse path metric calculation means 4 calculates the reverse path metric.

  The values read from the test bit sequence 2 storage means 13 and the interleaved order external information storage means 22 at the addresses of the forward read address generation means 32 and the forward read address generation means 34 are the switching means 36 and the switching means. The selection is made at 37 and inputted to the forward branch metric calculation means 6. The forward branch metric calculation means 6 calculates a forward branch metric, and the forward path metric calculation means 7 calculates a forward path metric.

  The LLR calculation unit 8 includes the forward branch metric calculated by the forward branch metric calculation unit 6, the forward path metric calculated by the forward path metric calculation unit 7, and the description in the fifth embodiment. The external information series is calculated from the reverse path metric read from the reverse path metric storage means 5 by the address of the read address generation means 39 generated in the procedure. The address of the external information write address generation means 35 is set to the (M (i-2))-th address in a turbo interleave table (not shown), and the external information series is written to the received bit series order external information storage means 21.

  Thereafter, the address of the reverse direction read address generation means 31 is sequentially set to the previous address in the turbo interleave table, and the address of the reverse direction read address generation means 33 is counted down to ((M−1) i). Further, the address of the forward direction read address generation means 32 is sequentially set to the next address in the turbo interleave table, and the address of the forward direction address generation means 34 is counted up to (M (i−1) −1). Further, the address of the external information write address generation means 35 is sequentially set to the next address in the turbo interleave table, the external information series is sequentially calculated and written in the received bit series order external information storage means 21.

  For the last block K, the address of the forward read address generating means 32 is set to the (M (K-1)) th address in the turbo interleave table, and the address of the forward read address generating means 34 is set to (M (K -1)). Then, the information bit sequence, the check bit sequence 2 and the external information sequence are read from the information bit sequence storage unit 11, the check bit sequence 2 storage unit 13 and the interleave order external information storage unit 22, respectively.

  The values read from the check bit sequence 2 storage means 13 and the interleaved order external information storage means 22 at the addresses of the forward read address generation means 32 and the forward read address generation means 34 are switched by the switching means 36 and the switching means 37. It is selected and input to the forward branch metric calculation means 6. The forward branch metric calculation means 6 calculates a forward branch metric, and the forward path metric calculation means 7 calculates a forward path metric.

  The LLR calculation unit 8 includes the forward branch metric calculated by the forward branch metric calculation unit 6, the forward path metric calculated by the forward path metric calculation unit 7, and the description in the fifth embodiment. The external information series is calculated from the reverse path metric read from the reverse path metric storage unit 5 by the address of the read address generation unit 39 generated in the procedure, and the interleaving order designated by the external information write address generation unit 35 Write to the address of the external information storage means 22.

  Thereafter, the address of the forward read address generating means 32 is sequentially set to the next address in the turbo interleave table, and the address of the forward read address generating means 34 is counted up to (N-1). Further, the address of the external information write address generation means 35 is sequentially set to the next address in the turbo interleave table.

  The above process is repeated a predetermined number of times, and the hard decision decoding sequence that is finally output by the LLR calculating unit 8 is output as the decoding result 102.

  As described above, according to the sixth embodiment, as in the first embodiment, the start position of the path metric calculation in the reverse direction can be easily determined regardless of the code length N. It is done.

  Further, according to the sixth embodiment, the reverse direction read address generation unit 31, the forward direction read address generation unit 32, the reverse direction read address generation unit 33, the forward direction read address generation unit 34, and the external information write address generation unit 35. However, the read address and write address for the information bit sequence storage unit 11, the check bit sequence 1 storage unit 12, the check bit sequence 2 storage unit 13, the received bit sequence order external information storage unit 21 and the interleaved order external information storage unit 22 are described above. By generating the information bit sequence as described above, it is possible to configure the information bit sequence with a common storage unit without storing the interleaved sequence and the non-interleaved sequence in separate storage units, and it is possible to reduce the storage capacity. .

  Note that the same effect can be obtained for the sixth embodiment even if decoding is performed in the decoding procedure of the second embodiment.

  As described above, the turbo code error correction decoding method according to the present invention is suitable for easily determining the path metric calculation start position in the reverse direction regardless of the code length N.

Claims (8)

A code length N turbo code reception sequence is separated into an information bit sequence, a check bit sequence 1 corresponding to an uninterleaved encoder, and a check bit sequence 2 corresponding to an interleaved encoder. In the error correction decoding method of turbo code that performs the soft input soft output decoding process by calculating the reverse path metric and the forward path metric for each of the divided blocks,
Each separated sequence is selected for every M symbols from the top to form one block and divided into K blocks, the block length from block 1 to block (K-1) is made up of M symbols, and the last An error correction decoding method for turbo codes, characterized in that the block length of the block K is configured to be (NM (K-1)) symbols. The backward path metric calculation learning is performed using the first L symbols in the M symbols of the subsequent block when calculating the backward path metric of each block. An error correction decoding method for a turbo code according to claim. The soft input / soft output decoding process corresponding to an interleaved encoder is performed after the soft input / soft output decoding process corresponding to an uninterleaved encoder as the soft input / soft output decoding process for each block. A turbo code error correction decoding method according to claim 1. The soft input / soft output decoding process corresponding to an encoder without interleaving is performed after the soft input / soft output decoding process corresponding to an interleaved encoder as the soft input / soft output decoding process for each block. A turbo code error correction decoding method according to claim 1. When tail bits are added to a turbo code reception sequence having a code length N, the tail bits are used when calculating the path metric in the reverse direction of the block (K-1) and the last block K. The turbo code error correction decoding method according to claim 1, wherein learning of path metric calculation in the reverse direction is performed. When calculating the forward path metric, the forward path metric at the end of each block is held and used as an initial value when calculating the forward path metric of the next block. The turbo code error correction decoding method according to claim 1. When storing the calculated reverse path metric of each block in the reverse path metric storage means in the soft input soft output decoding process, the address of the reverse path metric storage means is set in ascending order according to the block number of each block. 2. The turbo code error correction decoding method according to claim 1, wherein the turbo code error correction decoding method is generated alternately in descending order. Information bit sequence storage means for storing an information bit sequence separated from a reception sequence of a turbo code of code length N, and a check bit for storing a check bit sequence 1 corresponding to an uninterleaved encoder separated from the reception sequence Sequence 1 storage means, check bit sequence 2 storage means for storing check bit sequence 2 corresponding to an interleaved encoder separated from the received sequence, information bit sequence storage means, check bit sequence 1 storage means In addition, each sequence stored in the check bit sequence 2 storage means is selected for every M symbols from the top to constitute one block and divided into K blocks, and from block 1 to block (K-1) The block length of the last block K is composed of M symbols, and the block length of the last block K is composed of (N−M (K−1)) symbols. A received bit sequence for storing the external information sequence calculated by calculating the reverse path metric and the forward path metric for each divided block and performing the soft input / soft output decoding process in the order of the received bit sequence Sequential external information storage means, and interleaved order external information storage means for storing the external information series in interleaved order,
Read addresses of the information bit sequence storage means, the reception bit sequence order external information storage means and the interleave order external information storage means for the reverse path metric calculation and the forward path metric calculation are separately generated and Separately generating read addresses of the check bit sequence 1 storage means and the check bit sequence 2 storage means for the direction path metric calculation and the forward path metric calculation, the received bit sequence order external information storage means, Generate a write address for writing the external information sequence in the interleaved order external information storage means, select an output from the check bit series 1 storage means or the check bit series 2 storage means, and receive the received bit series order external information Select the output from the storage means or the interleaved order external information storage means, and The output from the bit sequence storage means, reverse path metric calculation and forward path metric calculation error correcting decoder of the turbo code and performs.

Images