JPS649558A - Bus arbitrating circuit - Google Patents

Bus arbitrating circuit

Info

Publication number
JPS649558A
JPS649558A JP16393687A JP16393687A JPS649558A JP S649558 A JPS649558 A JP S649558A JP 16393687 A JP16393687 A JP 16393687A JP 16393687 A JP16393687 A JP 16393687A JP S649558 A JPS649558 A JP S649558A
Authority
JP
Japan
Prior art keywords
priority
lowest
highest
bus control
control right
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP16393687A
Other languages
Japanese (ja)
Inventor
Mitsuhiko Koike
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fuji Electric Co Ltd
Original Assignee
Fuji Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fuji Electric Co Ltd filed Critical Fuji Electric Co Ltd
Priority to JP16393687A priority Critical patent/JPS649558A/en
Publication of JPS649558A publication Critical patent/JPS649558A/en
Pending legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14—Handling requests for interconnection or transfer
    • G06F13/36—Handling requests for interconnection or transfer for access to common bus or bus system

Abstract

PURPOSE:To eliminate the local biasing of the system performance by incrementing the priority of each device (decrementing) by one every time device acquires a bus control right, and providing a priority revision circuit bringing the lowest (highest) priority of a device to the highest (lowest) as a result. CONSTITUTION:Every time any SCSI (Small Computer System Interface) device acquires a bus control right, the priority of each device is incremented (decremented 1) by 1 and the priority revision circuit 2 is provided, which brings the priority of the device whose priority reaches the lowest (highest) into the highest (lowest) as the result. Thus, a disadvantage of awaiting the acquisition of the priority is eliminated and the disadvantage of a SCSI device cannot acquire the bus control right for a long time by chance is eliminated.
JP16393687A 1987-07-02 1987-07-02 Bus arbitrating circuit Pending JPS649558A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP16393687A JPS649558A (en) 1987-07-02 1987-07-02 Bus arbitrating circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP16393687A JPS649558A (en) 1987-07-02 1987-07-02 Bus arbitrating circuit

Publications (1)

Publication Number Publication Date
JPS649558A true JPS649558A (en) 1989-01-12

Family

ID=15783637

Family Applications (1)

Application Number Title Priority Date Filing Date
JP16393687A Pending JPS649558A (en) 1987-07-02 1987-07-02 Bus arbitrating circuit

Country Status (1)

Country Link
JP (1) JPS649558A (en)

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