JPS6489833A - Code error rate calculation device - Google Patents

Code error rate calculation device

Info

Publication number
JPS6489833A
JPS6489833A JP24721787A JP24721787A JPS6489833A JP S6489833 A JPS6489833 A JP S6489833A JP 24721787 A JP24721787 A JP 24721787A JP 24721787 A JP24721787 A JP 24721787A JP S6489833 A JPS6489833 A JP S6489833A
Authority
JP
Japan
Prior art keywords
interference
processing unit
central processing
adjacent channels
effect
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP24721787A
Other languages
Japanese (ja)
Inventor
Shunsuke Hayashi
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Mitsubishi Electric Corp
Original Assignee
Mitsubishi Electric Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Mitsubishi Electric Corp filed Critical Mitsubishi Electric Corp
Priority to JP24721787A priority Critical patent/JPS6489833A/en
Publication of JPS6489833A publication Critical patent/JPS6489833A/en
Pending legal-status Critical Current

Links

Abstract

PURPOSE:To obtain a simulator enabling to simulate a transmission quality of a PSK signal wave while taking the effect of an interference wave such as adjacent channel interference into consideration by providing a central processing unit calculating the quantity of interference between adjacent channels. CONSTITUTION:A 3rd central processing unit 6 calculates the interference quantity between adjacent channels and the result of calculation is stored in a 2nd storage device 7 together with a parameter representing the quantity of effect of white gauss noise and intercode interference calculated by a 2nd central processing unit 5. A 4th central processing unit 8 calculates the parameter representing white gauss noise and intercode interference quantity stored in the 2nd storage device 7 and the code error rate of a required PSK(phase shift keying) signal wave from the interference between adjacent channels. Thus, the transmission quality of the PSK signal wave is simulated by taking even the effect of interference such as interference between adjacent channels into consideration.
JP24721787A 1987-09-30 1987-09-30 Code error rate calculation device Pending JPS6489833A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP24721787A JPS6489833A (en) 1987-09-30 1987-09-30 Code error rate calculation device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP24721787A JPS6489833A (en) 1987-09-30 1987-09-30 Code error rate calculation device

Publications (1)

Publication Number Publication Date
JPS6489833A true JPS6489833A (en) 1989-04-05

Family

ID=17160188

Family Applications (1)

Application Number Title Priority Date Filing Date
JP24721787A Pending JPS6489833A (en) 1987-09-30 1987-09-30 Code error rate calculation device

Country Status (1)

Country Link
JP (1) JPS6489833A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH08288796A (en) * 1995-04-11 1996-11-01 Nec Corp Automatic frequency control circuit

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH08288796A (en) * 1995-04-11 1996-11-01 Nec Corp Automatic frequency control circuit

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