JPS6488790A - Straight line drawing system - Google Patents

Straight line drawing system

Info

Publication number
JPS6488790A
JPS6488790A JP24436387A JP24436387A JPS6488790A JP S6488790 A JPS6488790 A JP S6488790A JP 24436387 A JP24436387 A JP 24436387A JP 24436387 A JP24436387 A JP 24436387A JP S6488790 A JPS6488790 A JP S6488790A
Authority
JP
Japan
Prior art keywords
straight line
bits
line drawing
speed
cycle
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP24436387A
Other languages
Japanese (ja)
Inventor
Tsuyoshi Igarashi
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Toshiba Corp
Original Assignee
Toshiba Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Toshiba Corp filed Critical Toshiba Corp
Priority to JP24436387A priority Critical patent/JPS6488790A/en
Publication of JPS6488790A publication Critical patent/JPS6488790A/en
Pending legal-status Critical Current

Links

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  • Image Generation (AREA)

Abstract

PURPOSE:To draw a straight line at high speed by performing linear coordinate generation at the cycle of a T with a DDA (straight line generator), when the memory cycle of a frame memory is at N.T (N=2<n>, an (n) is the number of low-order bits). CONSTITUTION:At the last 1T of the cycle N.T, a true value is set without fail at a bit position corresponding to the linear coordinates for the N point generated between the period of the N.T from a straight line generator 13 out of the respective bit positions of holding means 16 and 17. Consequently, by using the held data of the holding means 16 and 17, the straight line drawing for the N point to for a 2<n>X2<m> bit area in the frame memory indicated by the residual bits excluding the low-order (n) bits and (m) bits of X and Y coordinates generated by the straight line generator 13 can be performed in a lump. Thus, a straight line drawing speed does not suppressed by the speed of the low frame memory, and the straight line drawing can be performed at high speed, which is the original speed of the DDA 13.
JP24436387A 1987-09-30 1987-09-30 Straight line drawing system Pending JPS6488790A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP24436387A JPS6488790A (en) 1987-09-30 1987-09-30 Straight line drawing system

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP24436387A JPS6488790A (en) 1987-09-30 1987-09-30 Straight line drawing system

Publications (1)

Publication Number Publication Date
JPS6488790A true JPS6488790A (en) 1989-04-03

Family

ID=17117578

Family Applications (1)

Application Number Title Priority Date Filing Date
JP24436387A Pending JPS6488790A (en) 1987-09-30 1987-09-30 Straight line drawing system

Country Status (1)

Country Link
JP (1) JPS6488790A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8503354B2 (en) 2006-11-07 2013-08-06 Nokia Corporation Control signaling techniques for wireless networks

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8503354B2 (en) 2006-11-07 2013-08-06 Nokia Corporation Control signaling techniques for wireless networks

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