JPS648767B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a bar graph display device that displays various measured quantities in bar graphs.

In recent years, display devices such as liquid crystal display devices and fluorescent display devices have been incorporated into meter panels (instrument panels) installed in the driver's seat of automobiles, and for example, as shown in FIG. a vehicle speed display section 3 consisting of a section 2;
A vehicle display device equipped with an engine speed display section 6 consisting of a bar graph display section 4 and a numerical display section 5 similar to the above is mounted on a vehicle, and the vehicle speed and engine speed of the vehicle can be displayed in a bar graph or digital format. Display is being done.

Conventionally, the bar graph display section 1 of the vehicle speed display section 3 and the bar graph display section 4 of the engine rotation speed display section 6 have opposing glass surfaces, although not specifically shown, in the case of a liquid crystal display device. A large number of segment electrodes for bar graph display formed on one glass surface of a liquid crystal cell and a common electrode formed on the other glass surface are opposed to each other with a liquid crystal layer filled in the liquid crystal cell in between. Along with letting
Segment electrode terminals and common electrode terminals are drawn out from these segment electrodes and common electrodes, respectively, and a voltage having an opposite phase to the voltage waveform applied to the common electrode is applied to the segment electrodes that display the bar graph, while displaying the bar graph. A voltage waveform having the same phase as that of the common electrode is applied to the segment electrodes that are not used, or static drive is performed to fix the potential of the common electrode.

By the way, the normal vehicle speed when a car is running is at most about 80 km/h or less, and it is almost impossible to drive at a speed exceeding 80 km/h, but the bar graph display section 1 of the vehicle speed display section 3 is When static driving is used, segment electrode terminals must be drawn out from each segment electrode in areas exceeding 80 km/h where display operations are rarely performed, resulting in a very large number of segment electrode terminals. Therefore, there was a drawback that the cost of the bar graph display device increased.

An object of the present invention is to provide a bar graph display device with a small number of segment electrode terminals and low cost.

For this reason, the present invention provides a bar graph display device that arranges a plurality of display segments in a band shape and displays an amount of input information as a bar graph. and a second display area subsequent to the first display area, the segment corresponding to the first display area is statically driven, and the segment corresponding to the second display area is dynamically driven. There is.

Hereinafter, the present invention will be described in detail with reference to the accompanying drawings.

In Figure 2, 11 is a car (not shown).
It is a bar graph display section that displays the vehicle speed on a liquid crystal display, and S ₀ , S ₁ , S ₂ , ..., S ₆₃ are segment electrodes, C ₀ ,
C ₁ is a common electrode, N ₁₀ , N ₂₀ , ..., N ₁₆₀ are arranged along the segment electrodes S ₀ , S ₁ , S ₂ , ..., S ₆₃ , and the numbers "10", "20", ..., These are number segment electrodes that each display "160".

The segment electrodes S ₀ , S ₁ , S ₂ ,..., S ₆₃ are as follows:
A numeric segment electrode is placed on one glass surface of a liquid crystal cell (not shown) having opposing glass surfaces.
Together with N ₁₀ , N ₂₀ , . . . , N ₁₆₀ , the bar graph display section 1 of the vehicle speed display section 3 shown in FIG. 1 is formed as an example.

On the other hand, common electrodes C ₀ and C ₁ are formed on the other glass surface of the liquid crystal cell.

The common electrode C ₀ is selected among the 64 segment electrodes S ₀ , S ₁ , S ₂ , ..., S ₆₃ when the vehicle speed is in the normal range of 0 Km/h to 80 Km/h. 32 with high display frequency
Segment electrodes S ₀ , S ₁ , S ₂ , ..., S ₃₁ and numerical segment electrodes N ₁₀ , N ₂₀ , ..., N ₈₀ are opposed to each other with a liquid crystal layer (not shown) in between.

Another common electrode C ₁ faces the remaining segment electrodes S ₃₂ , S ₃₃ , ..., S ₆₃ and numerical segment electrodes N ₉₀ , N ₁₀₀ , ... N ₁₆₀ with a liquid crystal layer (not shown) in between.

P ₀₃₂ , P ₁₃₃ , P ₂₃₄ , ..., P ₃₁₆₃ are all segment electrode terminals, and segment electrode terminal P ₀₃₂
is segment terminal S ₀ and S ₃₂ , segment terminal
P ₁₃₃ is electrically connected to segment electrodes S ₁ and S ₃₃ , ..., segment terminal P ₃₁₆₃ is electrically connected to segment electrodes S ₃₁ and S ₆₃ , respectively.

Further, P ₀ is a common electrode terminal that is electrically connected to the common electrode C ₀ , P ₁ is a common electrode terminal that is electrically connected to another common electrode C ₁ , and P ₃ is a numeric segment electrode N ₁₀ , N ₂₀ ,...,N It is a number segment electrode terminal that conducts to ₁₆₀ .

The bar graph display section 11 is controlled by the circuit shown in FIG.

In FIG. 3, 21 is a data memory, 22 is a multiplexer, 23 is a segment driver, 2
4 is a controller, 25 is a reference voltage generation circuit, 2
6 is a common driver.

The data memory 21 is a circuit that latches the bar graph signal inputted from a conversion circuit (not shown) that converts the vehicle speed of the automobile into a bar graph signal for displaying a bar graph. The 64 output terminals REGφ, REG1, ..., correspond to the 64 segment electrodes S ₀ , S ₁ , S ₂ , ..., S ₆₃ of the bar graph display section 11, respectively.
It has REG63.

In the data memory 21, as the speed of the car increases, the potential of the output terminal with a large subscript becomes "High" one after another, and for example, when the speed of the car is 80 km/h.
In the case of , output terminal REGφ, REG1,…, REG
31 are respectively “High” and the vehicle speed is 160km/h, the output terminals REGφ and REG
1,..., REG63 all become "High".

Above output terminal REGφ, REG1,..., REG63
The respective outputs are input to transfer gates 100, 101, . . . , 163 of the multiplexer 22, respectively.

The above transfer gates 100, 101,...,
163 are all well-known CMOS switches,
These transfer gates 100, 101,...,
163 is turned on when its control input is "High" and turned off when it is "Low".

The above transfer gates 100, 101,...,
Of 163, transfer gate 100,10
1, . . . , 131 are controlled by the output of a JK flip-flop 27 of a controller 24, which will be described later, and the remaining transfer gates 132, 133, .
It is controlled by the Q output of the JK flip-flop 27 mentioned above.

The above transfer gates 100, 101,...,
131 output terminals and transfer gate 1
The respective output terminals of 32, 133, ..., 163 are connected at connection points J ₀₃₂ , J ₁₃₃ , ..., J ₃₁₆₃ , and depending on the potential level of these connection points J ₀₃₂ , J ₁₃₃ , ..., J ₃₁₆₃ ,
The next segment driver 23 is controlled.

The segment driver 23 is a circuit that controls passage of the segment drive signals φ ₁ and ₁ output from the reference voltage generation circuit 25 based on the output of the multiplexer 22, and is connected to the connection point J ₀₃₂ ,
Depending on the potential level of J ₁₃₃ ,…, J ₃₁₆₃ , it is turned on,
Transfer gates 20 each of which is controlled to turn off
0,201,...,231, the above connection points J ₀₃₂ , J ₁₃₃ ,
..., J ₃₁₆₃ , the on/off state of which is controlled by the outputs of inverters 300, 301, ...331, which invert the potential levels of J 3163, respectively.
00, 401, . . . , 431 and the above-mentioned inverters 300, 301, . . . , 331.

The above transfer gates 200, 201,...,
231 receives a segment drive signal φ ₁ as shown in FIG.
1,..., 431, the reference voltage generation circuit 25
, a segment drive signal ₁ as shown in FIG. 4C is input.

The above transfer gates 200, 201,...,
Each output terminal of 231 is connected to the segment electrode terminals P ₀₃₂ , P ₁₃₃ , ..., P ₃₁₆₃ of the bar graph 11, respectively, and the transfer gates 400, 401,
..., 431 are also connected to the segment electrode terminals P ₀₃₂ , P ₁₃₃ , ..., P ₃₁₆₃ , respectively.

On the other hand, the reference voltage generation circuit 25 includes resistors R,
R, clock pulse oscillator 2 of controller 24
The transfer gates 31 and 32 are turned on and off by the clock output from the transfer gate 8, and the transfer gates 31 and 32 are turned on and off by the output of the inverter 35 which inverts the clock pulse.
It consists of transfer gates 33 and 34 that are turned off and the inverter 35 mentioned above.

The resistors R and R are connected in series between a terminal 12 having a potential of V _CLD1 and a terminal 13 having a potential of V _CLD3 , and from the connection point _J0 of these resistors R and R, a potential of V _CLD2 is connected. A reference potential signal φ ₀ as shown in FIG. 4 is outputted.

Generally, the above potentials V _CLD1 , V _CLD2 and V _CLD3 are
As is well known, V _Th is the threshold of the absorption characteristic of the liquid crystal element, V ^** _LC is the allowable voltage applied between the electrodes of the liquid crystal element when not driven, and V _LC is the maximum voltage when driven. For example, |V _LC |=V _LCD1 −V _LCD3 >V _Th |V ^** _LC |=V _LCD1 −V _LCD2 =V _LCD2 −V _LCD3 <V _Th .

The above potential V _CLD1 is the transfer gate 31, 3
4 is applied to each input terminal, and the potential
V _CLD3 is applied to each input terminal of transfer gates 32 and 33, respectively.

The outputs of the transfer gates 31 and 33 are:
Transfer gates 200, 20 of segment driver 23 as segment drive signal _φ1
1, ..., 231, respectively, and the outputs of the transfer gates 32 and 34 are input as the segment drive signal ₁ to the transfer gates 400, 401, ..., 431 of the segment driver 23 and the transfer gates 41, 41, of the common driver 26, which will be described next. 42 respectively.

The common driver 26 is connected to the controller 24
The transfer gates 41 and 4 are controlled on and off by the output _φ2 of the JK flip-flop 27.
2 and the transfer gate 4 which is controlled on and off by the Q output ₂ of the JK flip-flop 27.
3, 44, transfer gates 41 and 4
The output terminals of transfer gates 42 and 44 are connected to the common electrode terminal P ₀ and the output terminals of the transfer gates 42 and 44 are respectively connected to the common electrode terminal P ₁ .

The controller 24 consists of a JK flip-flop 27 and a clock oscillator 28.

The above-mentioned JK flip-flop 27 is a toggle flip-flop that operates by applying a "High" level voltage to its J input terminal and K input terminal and toggling by the clock pulse shown in FIG. It makes up the group.

The output of the output terminal REG31 of the data memory 21 is input to the reset terminal R of the JK flip-flop 27, and when the potential of the output terminal REG31 is "Low", the JK flip-flop 27
is reset and the bar graph display section 11 is statically driven, and when it is "High", the JK flip-flop 27 is released from reset and the bar graph display section 11 is dynamically driven.

Next, the operation shown in FIG. 3 will be explained.

When the circuit shown in FIG. 3 is operating, the clock pulse oscillator 28 of the controller 24 outputs the clock pulse shown in FIG. 4A.

The clock pulses are applied to the transfer gates 31, 32 and 33, 34 of the reference voltage generating circuit 25.
Turn on and off respectively, transfer gate 3
1 and 33, the segment drive signal φ ₁ as shown in FIG.
Segment drive signals ₁ as shown in FIG. 4C are outputted from 2 and 34, respectively.

Now, the car is stopped and its speed is 0 km/
h, the output terminal of the data memory 21
REG0, REG1, ..., REG63 are all "Low", and transfer gates 200, 201, ..., 231 of the segment driver 23 are all turned off, whereas transfer gates 400, 401, ..., 431 are turned off. Turn on both.

Therefore, the segment drive signal ₁ shown in FIG. 4C is applied to the segment electrodes _S0 , _S1 ,..., _S31 , _S32 , _S33 ,..., _S63 of the bar graph display section 11 ( (See Figure 4, L and O).

On the other hand, the JK flip-flop 27 of the controller 24 is connected to the output terminal REG3 of the data memory 21.
1 is “High” (vehicle speed is 80km/h)
) is reset until its Q output ₂
The output φ ₂ is “Low” and “High” as shown in FIG.
1, 44 are on, transfer gates 42, 43
is turned off.

By turning on the transfer gate 41, the common electrode _C0 of the bar graph display section 11 has the fourth
As shown in figure wa, segment drive signal ₁
is applied, and the transfer gate 44
By turning on the common electrode C ₁ of bar graph 11
As shown in Fig. 4, the reference potential signal ₀
is applied.

From the above, the same phase drive voltage is applied to the segment electrodes S ₀ , S ₁ , ..., S ₃₁ of the bar graph display section 11 and the common electrode C ₀ , and the common electrode C ₁
The reference potential signal φ ₀ will be applied to
None of the segment electrodes of the bar graph display section 11 performs a display operation.

Next, the car travels 80km/km between time t ₁ and time t ₂ .
Assuming that the vehicle is traveling at a speed of less than h, for example 60 km/h, the output terminal of the data memory 21
Among REG ₀ , REG ₁ , …, REG ₆₃ , the output terminal
The output terminals from REG ₀ to REG ₂₃ are "High", and the remaining output terminals from REG 24 to REG ₆₃ are "Low" (see Figure 4), and the JK flip-flop 27 of the controller 24 is the same as when the vehicle speed is zero. It remains reset.

Since the JK flip-flop 27 is reset, the transfer gates 100, 101, . . . , 131 of the multiplexer 22 are turned on.
Transfer gate 132, 133,..., 163
is turned off.

From the above, transfer gates 100 to 12
3 become "High", and the transfer gates 200 to 223 of the segment driver 23 are turned on.

In addition, each output of the transfer gates 124 to 133 becomes "Low", and the outputs of the transfer gates 424 to 4 of the segment driver 23 become "Low".
31 turns on.

Therefore, the segment drive signal φ ₁ is applied from the reference voltage generation circuit 25 to the segment electrodes S ₀ to S ₂₃ and the segment electrodes S ₃₂ to S ₅₅ of the bar graph 11, as shown in FIG. ,
The segment drive signal ₁ is applied from the reference voltage generation circuit 25 to the segment electrodes S ₂₄ to S ₃₁ and the segment electrodes S ₅₆ to S ₆₃ of the bar graph 11, as shown in FIG. 4E.

On the other hand, at this time, the JK flip-flop 27 of the controller 24 has been reset as described above, so its Q output ₂ and output ₂ are
As shown in Figure 4 E and D, respectively, they are "Low" and "High", and the common driver 2
Transfer gates 41 and 44 of No. 6 are turned on, and transfer gates 42 and 43 are turned off.

By turning on the transfer gate 41, the common electrode _C0 of the bar graph display section 11 has the fourth
As shown in figure wa, segment drive signal ₁
is applied, and the transfer gate 44
By turning on, the reference potential signal φ ₀ is applied to the common electrode C ₁ of the bar graph display section 11, as shown in FIG.

From the above, segment drive signals φ 1 and 1 having opposite phases to each other are applied to the segment electrodes S ₀ to S ₂₃ and the common electrode C ₀ of the bar graph display section 11, respectively, whereas the segment drive signals φ ₁ and ₁ are applied to the segment electrodes S 0 to S _{23 of the bar graph display section 11 and the common electrode C 0} , respectively. The same segment drive signal ₁ as that of the common electrode C ₀ is applied to S 31 from S ₃₁ , and the reference potential signal φ ₀ is applied to the common electrode C ₁ (the fourth
(See figure B, H, R, O, WA, K).

Therefore, the above bar graph 11 indicates that only the liquid crystals between the segment electrodes S ₀ to S ₂₃ and the common electrode C ₀ are aligned in the direction of the electric field between these electrodes, and the vehicle speed is 60 km/h. is displayed using static drive, which allows clear display without display unevenness.

Next, when the vehicle speed of the automobile reaches 80 km/h at time _t2 and the output terminal REG31 of the data memory 21 becomes "High", the reset of the JK flip-flop 27 is released (see Fig. 4, T and R).

When the reset is released, the JK flip-flop 27 performs a frequency dividing operation to divide the clock pulse input to its trigger terminal T into 1/2 (see FIG. 4 D and H).

From time t ₂ to time t ₅ above, the car is operated at 80 kn/h.
When the vehicle is running at 100 kHz, the Q output ₂ and the output φ ₂ of the JK flip-flop 27 become "High" and "Low", respectively, between time t ₂ and time t ₃ (see Fig. 4, E and D). , transfer gates 100 to 131 of multiplexer 22 are turned off, and transfer gates 132 to 163 are turned on.

At this time, the output terminal REG of the data memory 21
0 to REG31 is “High”, output terminal REG32
to 63 are "Low", the outputs of the transfer gates 100 to 163 of the multiplexer 22 are all "Low", the transfer gates 400 to 431 of the segment driver 23 are turned on, and the segment electrodes S ₀ ,
Segment drive signal ₁ is applied to S ₁ , . . . , S ₆₃ from the reference voltage generation circuit 25 (see FIG. 4).

On the other hand, between the above-mentioned time _t2 and time _t3 , the transfer gates 43 and 4 of the common driver 26
2 are turned on, and the reference potential signal φ ₀ and the segment drive signal ₁ are applied to the common electrodes C ₀ and C ₁ of the bar graph display section 11, respectively (the fourth
(See Figures W and F).

From the above, between time _t2 and time _t3 , the reference potential signal _φ0 is applied to the common electrode _C0 of the bar graph display section 11, and the segment electrodes _S32 , _S33 ,...,
Segment drive signal ₁ is applied to both S ₆₃ and common electrode C ₁ , and the display on bar bluff display section 11 disappears.

Next, between time _t3 and time _t4 , the Q output ₂ and the output _φ2 of the JK flip-flop 27 are "Low" and "High", respectively (see FIG. Agates 100 to 131 are turned on, and transfer gates 132 to 163 are turned off.

At this time, the output terminal REG of the data memory 21
0 to REG31 is “High”, output terminal REG13
Since transfer gates 2 to 163 are “Low”, transfer gates 100 to 13 of multiplexer 22
The output of transfer gate 1 becomes "High", the output of transfer gates 132 to 163 becomes "Low",
Transfer gate 2 of segment driver 23
00 to 231 are turned on.

By turning on the transfer gates 200 to 231, the segment electrodes S ₀ ,
A segment drive signal φ ₁ is applied to S ₁ , . . . , S ₆₃ from the reference voltage generation circuit 25 (see FIG.

On the other hand, between the above-mentioned time _t3 and time _t4 , the transfer gates 41 and 4 of the common driver 26
4 are respectively turned on, and the common electrode of bar graph 11
C ₀ and C ₁ each have segment drive signal ₁
and reference potential signal φ ₀ are applied (see Fig. 4,
).

From the above, between time t ₃ and time t ₄ , segment drive signals φ 1 and φ ₁ having mutually different phases are provided between segment electrodes S ₀ to S ₃₁ of bar graph display section ₁₁ and common electrode C 0. ₁ is applied to each, whereas a reference potential signal φ ₀ is applied to the common electrode _C1 , and a bar graph display corresponding to a vehicle speed of 80 km/h appears on the bar graph 11. .

Next, between time _t4 and time _t5 , the Q output ₂ and the output _φ2 of the JK flip-flop 27 of the controller 24 become "High" and "Low", respectively, so the display of the bar graph 11 disappears. Hereinafter, as long as the vehicle speed is 80 km/h, the display on the liquid crystal between the segment electrodes S ₀ to S ₃₁ of the bar graph display section 11 and the common electrode C ₀ will be JK.
In synchronization with the toggle operation of the flip-flop 27,
By repeating display and disappearance, the bar graph display section 11 dynamically displays the vehicle speed.

Next, at time t ₅ , the vehicle speed exceeds 80 km/h, and the output terminal REG0 of the data memory 21
It is assumed that up to REG32 becomes “High” (see Figure 4).

After the above time t ₅ , if the car is driven at a speed exceeding 80 km/h, between the above time t ₅ and time t ₆ , JK
The Q output ₂ and the output φ ₂ of the flip-flop 27 are “Low” and “High” respectively (the fourth
Transfer gates 100 to 131 of the multiplexer 22 are turned on, transfer gates ₁₃₂ to 163 are turned off, and the transfer gates of the multiplexer 22 are turned on and the transfer gates 132 to ₁₆₃ of the multiplexer 22 are turned off. Agate 100-13
The output of transfer gate 1 becomes "High", and the output of transfer gates 132 to 163 becomes "Low".

Therefore, the circuit of FIG. 3 performs the same operation as that between time t ₃ and time t ₄ , and the segment electrode
The bar graph display between S ₀ to S ₃₁ and the common electrode C ₀ appears, and the liquid crystal display between the segment electrodes S ₃₂ to S ₆₃ and the common electrode C ₁ disappears.

Between time _t6 and time _t7 , when the Q output ₂ and the output _φ2 of the JK flip-flop 27 become "High" and "Low", respectively (see FIG. 4, E and D), the transfer gate 100 of the multiplexer 22 to 131 are turned off, and transfer gates 132 to 163 are turned on.

At this time, the output terminal REG of the data memory 21
0 to REG32 is “High”, output terminal REG33
Since REG63 is "Low", only the output of transfer gate 132 of multiplexer 22 becomes "High".

Therefore, the segment driver 23 connects the transfer gate 200 and the transfer gate 40.
1 to 431 are respectively turned on, and the segment drive signal φ ₁ is applied to the segment electrodes S ₀ and S ₃₂ of the bar graph 11, while the segment electrode S ₁
Segment drive signal ₁ is applied to segment electrodes S ₃₃ to S 31 and segment electrodes S ₃₃ to S ₆₃ (see B, C, R, and O in FIG. 4).

On the other hand, between the above time t ₆ and time t ₇ , time t ₂
As in the case of and time t ₃ , the reference potential signal φ ₀ and the segment drive signal ₁ are applied to the common electrodes C ₀ and C ₁ of the bar graph 11, respectively (see FIG. 4 W and F).

From the above, between time t ₆ and time t ₇ , the reference potential signal φ ₀ is applied to the common electrode C ₀ of the bar graph display section 11, and the segment drive is applied to the segment electrode S ₃₂ and the common electrode C ₁ , respectively. Signals φ ₁ and ₁ are applied, and segment drive signal ₁ is applied from segment electrode S ₃₃ to segment electrode S ₆₃ , so that only the display by segment electrode S ₃₂ appears.

Hereinafter, the circuit of FIG. 3 alternately performs the operation between time t ₅ and time t ₆ and the operation between time t ₆ and time t ₇ in synchronization with the toggle operation of the JK flip-flop 27. A dynamic display is performed in which the vehicle speed is switched and displayed in the display area separated by the common electrodes _C0 and _C1 of the bar graph display section 11.

In this case, the display on the bar graph display section 11 is as follows.
Although the display is not as clear as in the case of the static drive described above, this does not pose a problem in practice since such display is performed infrequently.

If the bar graph display device is configured as described above, the display area of the bar graph 11 is divided into two according to the number of common electrodes C ₀ , C ₁ , so that 64 segment electrodes S ₀ , S ₁ , . . . It can be seen that it is sufficient to provide 1/2 the segment electrode terminals P ₀₃₂ , P ₁₃₃ , . . . , P ₃₁₆₃ for S ₆₃ .

In the above embodiment, the frequency of the clock pulse output from the clock pulse oscillator 28 for toggling the JK flip-flop 27 is as follows:
When dynamically driving the bar graph display section 11,
It is preferable to set the value to such a value that flickering of the display due to switching of display areas is not noticeable.

The present invention can be widely applied to bar graphs for displaying the speed of an automobile, bar graphs for displaying engine rotational speed, and bar graphs for displaying various measured quantities.

As is clear from the detailed description above, the present invention divides a plurality of display segments according to display areas, and drives these display areas using either static drive or dynamic drive depending on the size of input information. Since the bar graph can be displayed using the number of segment electrode terminals required to statically drive the regular display area, the number of segment electrode terminals drawn out from the segment electrodes is reduced, resulting in a low-cost bar graph display. A display device can be obtained. Furthermore, since the static drive and dynamic drive are switched depending on the magnitude of input information, the display in the commonly used area where the display frequency is high can be made clear and without display unevenness.

[Brief explanation of drawings]

FIG. 1 is a plan view of an automobile meter panel that displays a bar graph, FIG. 2 is an explanatory diagram of a bar graph display section of a bar graph display device according to the present invention, and FIG. 3 is an illustration of a bar graph display device according to the present invention. The circuit diagram and FIGS. 4A to 4F are time charts showing the operation of each part of FIG. 3, respectively. DESCRIPTION OF SYMBOLS 11... Bar graph display part, 21... Data memory, 22... Multiplexer, 23... Segment driver, 24... Controller, 25...
...Reference voltage generation circuit, 26...Common driver,
S ₀ , S ₁ , S ₂ ,..., S ₆₃ ... segment electrode, C ₀ ,
C ₁ ... Common electrode, P ₀₃₂ , P ₁₃₃ , ..., P ₃₁₆₃ ... Segment electrode terminal, P ₀ , P ₁ ... Common electrode terminal.

Claims (1)

[Claims] 1. In a bar graph display device that arranges a plurality of display segments in a band shape and displays an amount of input information as a bar graph, the plurality of display segments are arranged in a first display area corresponding to an initial area of bar graph display and a first display area corresponding to an initial area of the bar graph display.
A display device characterized in that it is divided into a second display area subsequent to the display area, and is configured to statically drive a segment corresponding to the first display area and dynamically drive a segment corresponding to the second display area. .