JPS648692A - Printed circuit board - Google Patents

Printed circuit board

Info

Publication number
JPS648692A
JPS648692A JP16228587A JP16228587A JPS648692A JP S648692 A JPS648692 A JP S648692A JP 16228587 A JP16228587 A JP 16228587A JP 16228587 A JP16228587 A JP 16228587A JP S648692 A JPS648692 A JP S648692A
Authority
JP
Grant status
Application
Patent type
Prior art keywords
patterns
plurality
lengths
wiring pattern
circuit board
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP16228587A
Inventor
Kazunobu Adachi
Giichi Oe
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date

Links

Classifications

    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00Printed circuits
    • H05K1/02Details
    • H05K1/0213Electrical arrangements not otherwise provided for
    • H05K1/0216Reduction of cross-talk, and noise or electromagnetic interference
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00Printed circuits
    • H05K1/02Details
    • H05K1/11Printed elements for providing electric connections to or between printed circuits

Abstract

PURPOSE:To regulating the length of a whole wiring pattern and to regulate a delay time by forming a single or a plurality of dummy wiring patterns for a wiring pattern for transmitting a signal, and disposing both so as to connect or separate them. CONSTITUTION:A plurality of dummy wiring patterns 5 are connected so as to be cut from a wiring pattern 4. Viaholes 6 are respectively formed near the cutting positions of the patterns 5. The lengths of the plurality of patterns 5 have different lengths, delay times corresponding to the lengths are known to minimize the number of connections or separations, and the delay time can be regulated accurately.
JP16228587A 1987-07-01 1987-07-01 Printed circuit board Pending JPS648692A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP16228587A JPS648692A (en) 1987-07-01 1987-07-01 Printed circuit board

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP16228587A JPS648692A (en) 1987-07-01 1987-07-01 Printed circuit board

Publications (1)

Publication Number Publication Date
JPS648692A true true JPS648692A (en) 1989-01-12

Family

ID=15751577

Family Applications (1)

Application Number Title Priority Date Filing Date
JP16228587A Pending JPS648692A (en) 1987-07-01 1987-07-01 Printed circuit board

Country Status (1)

Country Link
JP (1) JPS648692A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP1563573A2 (en) * 2002-11-20 2005-08-17 The Siemon Company Apparatus for crosstalk compensation in a telecommunications connector

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP1563573A2 (en) * 2002-11-20 2005-08-17 The Siemon Company Apparatus for crosstalk compensation in a telecommunications connector
EP1563573A4 (en) * 2002-11-20 2009-07-15 Siemon Co Apparatus for crosstalk compensation in a telecommunications connector

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