JPS6485412A - Frequency characteristic setting device - Google Patents

Frequency characteristic setting device

Info

Publication number
JPS6485412A
JPS6485412A JP24331687A JP24331687A JPS6485412A JP S6485412 A JPS6485412 A JP S6485412A JP 24331687 A JP24331687 A JP 24331687A JP 24331687 A JP24331687 A JP 24331687A JP S6485412 A JPS6485412 A JP S6485412A
Authority
JP
Japan
Prior art keywords
frequency characteristic
circuit
frequency
filter coefficient
group delay
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP24331687A
Other languages
Japanese (ja)
Inventor
Masaharu Matsumoto
Seiichi Ishikawa
Katsumasa Sato
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Panasonic Holdings Corp
Original Assignee
Matsushita Electric Industrial Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Matsushita Electric Industrial Co Ltd filed Critical Matsushita Electric Industrial Co Ltd
Priority to JP24331687A priority Critical patent/JPS6485412A/en
Publication of JPS6485412A publication Critical patent/JPS6485412A/en
Pending legal-status Critical Current

Links

Abstract

PURPOSE:To drastically reduce the arithmetic time obtaining a filter coefficient by dividing the frequency band into those corresponding to plural different sampling frequencies so as to reduce the number of processed data in each frequency band. CONSTITUTION:An input circuit 1 receives an optional group delay frequency characteristic, an integration circuit 2 uses a frequency to integrate the inputted group delay frequency characteristic and a split circuit 3 divides the phase frequency characteristic obtained by the circuit 2 into frequency bands corresponding to two different sampling frequencies. An arithmetic circuit 4 obtains the filter coefficient of FIR filters 5, 6 corresponding to the split phase frequency characteristic by the circuit 3 and the amplitude frequency characteristic corrected to bring the realized amplitude frequency characteristic to the unity. The sampling frequency of the FIR filters 5, 6 differ from each other and the number of the filter coefficient is the same. Then the arithmetic time to obtain the filter coefficient of the FIR filters to realize a desired group delay frequency characteristic is drastically reduced.
JP24331687A 1987-09-28 1987-09-28 Frequency characteristic setting device Pending JPS6485412A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP24331687A JPS6485412A (en) 1987-09-28 1987-09-28 Frequency characteristic setting device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP24331687A JPS6485412A (en) 1987-09-28 1987-09-28 Frequency characteristic setting device

Publications (1)

Publication Number Publication Date
JPS6485412A true JPS6485412A (en) 1989-03-30

Family

ID=17102022

Family Applications (1)

Application Number Title Priority Date Filing Date
JP24331687A Pending JPS6485412A (en) 1987-09-28 1987-09-28 Frequency characteristic setting device

Country Status (1)

Country Link
JP (1) JPS6485412A (en)

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6291011A (en) * 1985-10-17 1987-04-25 Victor Co Of Japan Ltd Digital graphic equalizer

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6291011A (en) * 1985-10-17 1987-04-25 Victor Co Of Japan Ltd Digital graphic equalizer

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