JPS648386B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Application of the Invention] The present invention relates to a recording processing method for a computer, and particularly to an improvement in a method for outputting information stored in a buffer memory.

[Background of the invention]

FIG. 1 is a block diagram showing a conventional recording processing method.

According to this conventional example, the resident memory MEM has two buffers 1 and 1, in order to guarantee continuous recording.
2 and a linkage table 3. The contents of buffers 1 and 2 are sent to an output file 13 (in this case, a magnetic tape M/T) via an output program 12 based on an output request program 10.
will be sent to.

The data flow in this type of device is as follows.

First, the output request program 10 stores processed data DT in the recording buffer 1, and stores and updates WP such as storage final address information in the linkage table 3.

Next, referring to the updated linkage table 3, if buffer 1 is full, set the bit to "1" to indicate that buffer 1 is full, and immediately set the M/T output program based on this event signal 11. 12.

Due to the buffer full event 11, the M/T output program 12 started from the output request program 10 first starts the linkage table 3
, the data of buffer 1 whose full indication bit is "1" is forcibly output to the output file (M/T) 13. After this output, the M/T output program 12 sets the fullness indicating bit of buffer 1 in the linkage table 3 to "0". When this full display bit becomes "0", the buffer becomes 1
becomes vacant again (writable state) and becomes a reserve for buffer 2. Below, buffers 1 and 2 will be used for cycling.

According to such a method, for example, for time t
The CPU load is as shown in curve 21 in Figure 2,
When a buffer full event occurs, output is immediately given to the output file 13. For this reason, even when the CPU load is close to its peak, for example at times t ₁ and t ₃ in FIG. 2, there is a drawback that the load 22 is further increased.

[Purpose of the invention]

An object of the present invention is to provide a recording processing method for a computer that can smooth the CPU load over time, avoid an extreme increase in the CPU load, and expect efficient CPU operation.

[Summary of the invention]

To achieve this objective, the present invention measures and predicts the CPU load when outputting information stored in the buffer memory of a computer, and outputs the stored information intensively when the CPU load is low. do as you like.

[Embodiments of the invention]

Embodiments of the present invention will be described below with reference to the accompanying drawings. In each figure, the same reference numerals indicate similar objects.

FIG. 3 shows an embodiment of this invention,
Similar to the conventional example shown in Fig. 1, the resident memory MEM is N
buffers 1 to n and linkage table 30
It is equipped with

However, one side of this recording buffer 1 to n is
The unit is a block to be output at one time, and has N sides, and each buffer 1 to n is sequentially and periodically used.

The data in the buffers 1 to n are output to the output file 39 by (1) the constant output program 31 or (2) the forced output program 38 based on the output request program 36.

The constant output program 31 is a CPU load measurement/prediction program 3 that operates based on the timer 35.
3, and its purpose is to output when the CPU is under low load.

The CPU load measurement/prediction program 33 measures and predicts the CPU load using a known method, and is, for example, as follows.

First, the load measurement is performed by setting the periodic activation signal 34 of the timer 35 to 100 times per second, and counting the count value by the program 33 sequentially from "1" for each periodic activation, and calculating the number of activations per second, that is, 1. Based on the count value per second, calculate the CPU load L _n as L _n = 100 - (count value).

Second, the load prediction is based on the current CPU load measurement value L _n and the previous value L _np , and calculates the predicted CPU load value L _P as follows: L _P = L _n + (L _np − L _n ) /T. However, T is the load measurement cycle.

The forced output program 38 forcibly sends out the output with the highest priority when the CPU is continuously in a high load state and data in buffers 1 to n cannot be output, thereby avoiding data loss.

The data DT1, DT2 from each program 31, 38 as described above, the measured value _Ln and the predicted value _LP of the CPU load are stored in a linkage table 30 having a structure as shown in FIG.

Next, the contents of the constant output program 31 and the forced output program 38 will be explained in more detail to clarify the contents of the present invention.

The constant output program 31 will be explained.

This program 31 is started by the start signal 32 of the CPU load measurement/prediction program 33 as described above, but the timing of this start is as follows.
This is when the predicted value of the CPU load is less than or equal to the low load reference value α.

Here, the reference value α is an average value of all CPU loads, taking into account the load due to output processing. On the other hand, β=
Introduce a criterion value β that is 0.6α.

FIG. 5 is a flowchart of a program 31 that starts with a reference value α and has a determination reference value β inside. Note that the numbers (1), (2), etc. in the following explanation correspond to each step number in the drawings.

When the predicted CPU load value L _P is less than or equal to α, the program 31 is started (1) and the linkage table 30
Import one block of data via (Figure 3)
(2). Next, find the predicted value L _P of the CPU load (3), and L _P
If it is β, the output data amount is multiplied by K (4) and data for K blocks is output, and if L _P > β, data for one block is output as is (5), and the output file 39 is (Fig. 3). After the data is filed, the linkage table 30
(Fig. 3) is updated (6), the output data amount is set to the initial value (7), and one cycle of operation is completed (8).

Fig. 6 shows an actual example of the CPU load versus time for such processing. Furthermore, curve 66
For example, based on the load measurements at times t ₁ and t ₂ ,
This is a prediction curve obtained at each time by obtaining the predicted value L _P at time _t3 .

Here, the measured value L _n at time t ₁ is the low load reference value α
is larger, but if the predicted value L _P is less than α, it is considered that the CPU load will decrease in the future, so 1
Data 65 for the block is output. Next, the time
At t ₂ , α>L _n >β, but since the predicted value L _P expected at time t ₃ is L _P <β, data 62 for K blocks are output. Thereafter, similarly, the output amount is controlled depending on the magnitude of the next predicted CPU load value, so that as much data as possible is output when the load is low.

The forced output program 38 will be explained.

This program 38 has a buffer page number M defined therein as a reference for activation. In other words, the forced output standard buffer surface number M out of the buffer surface number N
When it is full to (<N), program 3
8.

The forced output program 38 outputs K blocks of data at a time, and updates the currently used buffer surface number L and final read address information RP (Read Pointer) in the linkage table 30 after output.

On the other hand, after storing the data in the buffer, the output request program 36 updates the buffer surface number L and the storage final address information WP in the linkage table 30, and then compares the buffer surface number L with the storage final address information M, and as described above. Then, when L>M, the forced output program 38 is activated.

By the way, in order to realize the above processing configuration, it is necessary to determine the priority level of tasks in addition to mutual activation timing. FIG. 7 shows each task level in this embodiment.

According to the figure, when the task levels are 0 to 7 and 8, the forced output program 38 is given top priority over other processes, so it is designated as the highest priority level of level 0, and the constant output program 31 is , I set it to the lowest priority level, level 7, so that it would run during free time for other processes. By placing these at levels 0 and 7, the output request program 36 is enabled to operate regardless of output processing. Also,
The CPU load measurement/prediction program 33 is placed at level 6 in order to measure and predict the CPU load, excluding the load caused by the constant output program 31.

FIG. 8 is a flowchart showing the processing of another embodiment of the present invention, in which the constant output program 31
This corresponds to FIG. 5, which describes the above.

There are two differences between this embodiment and the embodiment shown in FIG.

One is that the CPU load change rate (81) has been newly added to the judgment condition. As a result, if the CPU load change rate tends to increase, the output amount can be controlled using the current measured value L _n instead of using the predicted value L _P (82).

The other is that when α<L _P <β, if the predicted value L _P approaches β, the output amount can be increased accordingly (83). Here, the load value that is the basis for prediction is
When the CPU change rate is negative, the conventional predicted value L _P is used,
When it is positive or 0, it is the measured value L _n . The amount of increase in the output amount is determined, for example, by providing a plurality of reference values between the reference values α and β, and increasing the output by k times when each reference value is below. Alternatively, since the reference values α to β are 1 to K blocks, they are determined by proportional calculation as shown in the following equation.

k=K×(α−L _P )/(β−α) The CPU load transition in the above case is as shown in FIG. 9, and smoothing can be further promoted.
In other words, the efficiency is even better than in the case of FIG.

Hereinafter, four modified examples will be explained.

First, below the low load reference value α, the number of output blocks may be varied by the predicted CPU load value L _P so that the total load including the CPU load due to output processing is below α.

Specifically, by pre-processing the output of one block,
Calculate the CPU load and use the predicted value L _P and reference value α
This method calculates how many blocks of data can be output between the two and controls the total CPU load to be below the reference value α. The formula for calculating the number of blocks is given by the following formula.

k=(α-L _P )/L ₁ Here, k is the number of blocks, and L ₁ is the CPU load required to output one block.

In this calculation of k, since it is necessary to convert k into an integer,
There are various possibilities such as rounding off, truncation, etc.

FIG. 10 shows the results of processing using this method, where k is determined by rounding down.

Second, if there is a fluctuation in the average value of the CPU load for a certain period, the low load reference value α is changed up and down as shown in FIG.

For example, on a daily, monthly, or yearly basis.
If there is a cycle, the reference value α is increased when the CPU load is high on average, and lowered when it is low, so that output processing can be performed on average.

Thirdly, as shown in Fig. 12, multiple layers of low load reference values are provided (in the case of the figure, there are five from α1 to α5),
The number of data output blocks can be determined for each layer.

For example, as shown in the figure, the low load reference value is α1
Five hierarchies are provided from ~α5, and the number of output blocks is sequentially increased to 5 blocks, such as 1 block when α1L _P >α2, 2 blocks when α2L _P >α3, and so on.

By doing so, output data can be smoothed with a simple configuration.

The fourth method is to introduce the following two processes.

In other words, as shown at time t ₁ in Figure 13, the CPU
The load change rate is negative (CPU load is decreasing), and
If the predicted CPU load value L _P is less than or equal to the reference value α, it is determined whether or not to output it based on the current measured CPU load value L _n .

Next, if the CPU load change rate is positive (CPU load is increasing) and the CPU load predicted value L _P is greater than or equal to the reference value α, determine whether to output or not based on the current CPU load measurement value L _n do.

Specifically, in the former case, the measured value L _n is compared with the output reference value α ₁ and is output when L _n ≦ α ₁ . In the latter case, it is output when L _n α ₂ .

According to such a method, the output determination near the boundary of the low load reference value α can be made more precise.

In any of the embodiments and modifications, the final change in CPU load over time is as shown in FIG. 14, in which data 142 is superimposed on a prediction curve 141.

〔Effect of the invention〕

According to this invention, by having the above configuration, the CPU load is smoothed over time,
It is possible to provide a recording processing method for a computer that avoids an extreme increase in CPU load and can be expected to efficiently operate the CPU.

In addition, by providing a forced output program, if a high load condition continues, the current CPU
Since data is sent immediately regardless of the load value, it is possible to avoid loss of recorded data that would otherwise occur due to such continuous high load conditions, and the reliability is high.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing a conventional processing method, FIG. 2 is a characteristic diagram showing the CPU load as a result of processing by the method in FIG. 1, FIG. 3 is a block diagram showing an embodiment of the present invention, and FIG. 5 and 5 are main part configuration diagrams of the embodiment of FIG. 3, FIG. 6 is a characteristic diagram showing the CPU load as a result of processing by the embodiment of FIG. 3, and FIG.
FIG. 8 is a block diagram showing other main parts of the embodiment shown in the figure, FIG. 8 is a system diagram of main parts of another embodiment of the present invention, and FIG.
FIGS. 10 to 13 are characteristic diagrams showing CPU loads as processing results according to the embodiment according to the present invention. FIG. FIG. 2 is a characteristic diagram showing a CPU load which is a general processing result according to the invention. 1-n...recording buffer, 30...linkage table, 31...output request program, 33
...CPU load measurement/prediction program, 35...
Timer, 36... Output request program, 38...
Forced output program, 39...output file,
MEM...Resident memory, α...Low load reference value.

Claims (1)

[Claims] 1. A recording buffer consisting of a plurality of blocks for storing sequentially arriving data, a first means for measuring and predicting the CPU load, and a reference value whose predicted value by the first means is predetermined. A recording processing method for a computer, comprising: second means that is activated in the following cases and sends the data stored in the buffer to an output file at a predetermined timing. 2 In the method described in claim 1,
A recording processing method for a computer, characterized in that the number of blocks of data taken out from the buffer varies depending on the measured value or predicted value by the first means. 3. A recording buffer consisting of a plurality of blocks that store sequentially arriving data, a first means for measuring and predicting the CPU load, and a system that is activated when the predicted value by the first means is less than a predetermined reference value. a second means for sending the data stored in the buffer to an output file at a predetermined timing; A recording processing method for a computer, comprising: third means for sending a block of data to the output file in place of the second means.