JPS6482262A - Logic symbol arranging method - Google Patents

Abstract

PURPOSE:To generate a low-order gate level logic diagram by obtaining the absolute position of each logic symbol in accordance with the position of a gate level logic diagram occupied area and the relative position of the logic symbol and arranging the logic symbol in this obtained position. CONSTITUTION:The size of the gate level logic diagram corresponding to each module and relative positions of logic symbols constituting the gate level logic diagram are preliminarily held in a table function module library 15. When the gate level logic diagram corresponding to each module is developed in a module arrangement position on a function logic diagram, the gate level logic diagram occupied area is secured in a data area 12C for logic diagram on the function logic diagram based on the data of the size of the gate level logic diagram stored in said table 15. It characterizes this method that the absolute position of each logic symbol is obtained in accordance with the position of the gate level logic diagram occupied area and the relative position of the logic symbol in the module and the logic symbol is arranged in this absolute position.