JPS6482260A - Delay analyzing system - Google Patents

Delay analyzing system

Info

Publication number
JPS6482260A
JPS6482260A JP62240400A JP24040087A JPS6482260A JP S6482260 A JPS6482260 A JP S6482260A JP 62240400 A JP62240400 A JP 62240400A JP 24040087 A JP24040087 A JP 24040087A JP S6482260 A JPS6482260 A JP S6482260A
Authority
JP
Japan
Prior art keywords
network model
delay
design
corrected
logical connection
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP62240400A
Other languages
Japanese (ja)
Inventor
Noriaki Hyodo
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp filed Critical NEC Corp
Priority to JP62240400A priority Critical patent/JPS6482260A/en
Publication of JPS6482260A publication Critical patent/JPS6482260A/en
Pending legal-status Critical Current

Links

Abstract

PURPOSE:To shorten the processing time required for delay analysis by extracting the difference between logical connection information and layout information before and after the change of design from a design data base to correct a delay network model. CONSTITUTION:A design data base difference extracting means 6 extracts the difference between logical connection information and layout information before and after the change of design of a logic circuit. A delay network model correcting means 1 corrects the generated delay network model based on logical connection information and wiring delay information before and after the change of design which are extracted by the means 6. A route instructing means 8 instructs the start point of a corrected route of the delay network model based on the extracted difference of logical connection information and layout information. A route tracing means 3 traces only the corrected route of the corrected delay network model having the start point instructed by the means 8 at the time of delay analysis of the corrected logic circuit.
JP62240400A 1987-09-25 1987-09-25 Delay analyzing system Pending JPS6482260A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP62240400A JPS6482260A (en) 1987-09-25 1987-09-25 Delay analyzing system

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP62240400A JPS6482260A (en) 1987-09-25 1987-09-25 Delay analyzing system

Publications (1)

Publication Number Publication Date
JPS6482260A true JPS6482260A (en) 1989-03-28

Family

ID=17058910

Family Applications (1)

Application Number Title Priority Date Filing Date
JP62240400A Pending JPS6482260A (en) 1987-09-25 1987-09-25 Delay analyzing system

Country Status (1)

Country Link
JP (1) JPS6482260A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6205573B1 (en) 1997-10-22 2001-03-20 Nec Corporation Delay analysis result display device

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6205573B1 (en) 1997-10-22 2001-03-20 Nec Corporation Delay analysis result display device

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