JPS6478517A - Digital system data slice circuit - Google Patents

Digital system data slice circuit

Info

Publication number
JPS6478517A
JPS6478517A JP23652087A JP23652087A JPS6478517A JP S6478517 A JPS6478517 A JP S6478517A JP 23652087 A JP23652087 A JP 23652087A JP 23652087 A JP23652087 A JP 23652087A JP S6478517 A JPS6478517 A JP S6478517A
Authority
JP
Japan
Prior art keywords
dropout
extended
signal
level
closed loop
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP23652087A
Other languages
Japanese (ja)
Inventor
Makoto Iida
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Panasonic Holdings Corp
Original Assignee
Matsushita Electric Industrial Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Matsushita Electric Industrial Co Ltd filed Critical Matsushita Electric Industrial Co Ltd
Priority to JP23652087A priority Critical patent/JPS6478517A/en
Publication of JPS6478517A publication Critical patent/JPS6478517A/en
Pending legal-status Critical Current

Links

Landscapes

  • Signal Processing For Digital Recording And Reproducing (AREA)
  • Manipulation Of Pulses (AREA)

Abstract

PURPOSE:To restore the level to a proper slice level after the end of dropout by increasing the clock frequency of an up-down counter by a dropout signal so as to increase the response of a closed loop system. CONSTITUTION:The closed loop system consists of a comparator 1, an up-down counter 2 and an A/D converter 3. A dropout signal is given to a dropout signal extending circuit 4 and outputted while being extended by a prescribed time. When the extended dropout signal is given to a clock frequency changeover circuit 5 and the extended dropout signal is at a high level, the high frequency clock is outputted as a sampling clock of the up-down counter 2. Thus, the response frequency of the closed loop system is increased for the extended dropout period only, the steep change in the DC component of the read signal is followed and the level is restored to a proper slice level after the end of dropout.
JP23652087A 1987-09-21 1987-09-21 Digital system data slice circuit Pending JPS6478517A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP23652087A JPS6478517A (en) 1987-09-21 1987-09-21 Digital system data slice circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP23652087A JPS6478517A (en) 1987-09-21 1987-09-21 Digital system data slice circuit

Publications (1)

Publication Number Publication Date
JPS6478517A true JPS6478517A (en) 1989-03-24

Family

ID=17001916

Family Applications (1)

Application Number Title Priority Date Filing Date
JP23652087A Pending JPS6478517A (en) 1987-09-21 1987-09-21 Digital system data slice circuit

Country Status (1)

Country Link
JP (1) JPS6478517A (en)

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5520008A (en) * 1978-07-28 1980-02-13 Nippon Telegr & Teleph Corp <Ntt> Digital signal receiving device
JPS60216627A (en) * 1984-04-12 1985-10-30 Toshiba Corp Digital data generating device

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5520008A (en) * 1978-07-28 1980-02-13 Nippon Telegr & Teleph Corp <Ntt> Digital signal receiving device
JPS60216627A (en) * 1984-04-12 1985-10-30 Toshiba Corp Digital data generating device

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