JPS6477221A - Semiconductor device - Google Patents
Semiconductor deviceInfo
- Publication number
- JPS6477221A JPS6477221A JP62234313A JP23431387A JPS6477221A JP S6477221 A JPS6477221 A JP S6477221A JP 62234313 A JP62234313 A JP 62234313A JP 23431387 A JP23431387 A JP 23431387A JP S6477221 A JPS6477221 A JP S6477221A
- Authority
- JP
- Japan
- Prior art keywords
- fets
- voltage
- circuit
- fet
- reference voltages
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Landscapes
- Logic Circuits (AREA)
- Electronic Switches (AREA)
Abstract
PURPOSE:To perform a quick operation by providing plural insulated gate (IG) FETs on a semiconductor substrate with a logic processing circuit between them and detecting reference voltages, which drive input and output logic circuits constituting of these FETs, to control the current consumption. CONSTITUTION:IG FETs M1 and M2 constitute the input logic circuit and IG FETs M3 and M4 constitute the output logic circuit on the semiconductor substrate with the logic processing circuit between them. An external pin reference voltage VS is supplied to a resistance R1 through an inductance LC, a wire resistance Rn, and an aluminum wire L to generate reference voltages VS1 and VS2. The voltage VS1 is connected to sources of the FET M2 and FETs M7 and M9 of a detecting circuit, and the voltage VS2 is connected to a current control FET M5. A constant voltage Vn inputted to gates of FETs M6 and M7 is set to a value lower than an input pin voltage Vad to obtain a detecting circuit output Vnoi. The voltage Vnoi is inputted to the gate of the FET M5 to control currents of FETs M3 and M4. Thus, the variance of reference voltages is suppressed to increase the power consumption, and the quick operation is stably performed.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP62234313A JP2845436B2 (en) | 1987-09-17 | 1987-09-17 | Semiconductor device |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP62234313A JP2845436B2 (en) | 1987-09-17 | 1987-09-17 | Semiconductor device |
Publications (2)
Publication Number | Publication Date |
---|---|
JPS6477221A true JPS6477221A (en) | 1989-03-23 |
JP2845436B2 JP2845436B2 (en) | 1999-01-13 |
Family
ID=16969049
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP62234313A Expired - Lifetime JP2845436B2 (en) | 1987-09-17 | 1987-09-17 | Semiconductor device |
Country Status (1)
Country | Link |
---|---|
JP (1) | JP2845436B2 (en) |
Citations (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS6432523A (en) * | 1987-07-27 | 1989-02-02 | Nippon Electric Ic Microcomput | Output buffer circuit |
-
1987
- 1987-09-17 JP JP62234313A patent/JP2845436B2/en not_active Expired - Lifetime
Patent Citations (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS6432523A (en) * | 1987-07-27 | 1989-02-02 | Nippon Electric Ic Microcomput | Output buffer circuit |
Also Published As
Publication number | Publication date |
---|---|
JP2845436B2 (en) | 1999-01-13 |
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