JPS6476256A - Bus adjusting device for multiplex input data transfer device - Google Patents

Bus adjusting device for multiplex input data transfer device

Info

Publication number
JPS6476256A
JPS6476256A JP23250187A JP23250187A JPS6476256A JP S6476256 A JPS6476256 A JP S6476256A JP 23250187 A JP23250187 A JP 23250187A JP 23250187 A JP23250187 A JP 23250187A JP S6476256 A JPS6476256 A JP S6476256A
Authority
JP
Japan
Prior art keywords
bus
time
timer
master
adjusting device
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP23250187A
Other languages
Japanese (ja)
Inventor
Kengo Fujiwara
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to JP23250187A priority Critical patent/JPS6476256A/en
Publication of JPS6476256A publication Critical patent/JPS6476256A/en
Pending legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14—Handling requests for interconnection or transfer
    • G06F13/36—Handling requests for interconnection or transfer for access to common bus or bus system

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Bus Control (AREA)

Abstract

PURPOSE:To apply no adverse influence to a system by applying an alarm to a specific bus master using a bus for more than a predetermined bus using limit time at the time of the elapse of a prescribed time and forcibly separating even at the time of no separation. CONSTITUTION:A bus adjusting device 6 multiplex processes a bus adjustment from the respective bus masters 2a, 2b,... to feed to a MPU1. A bus time out is detected by a first timer 8 for counting the bus using time after a certain bus master obtains the bus, a second timer 9 for counting the bus using time after this timer completes to count the prescribed time. When an alarm signal for releasing no bus even when the first timer counts the prescribed time is outputted and the second timer reaches a set time, the bus master is forcibly separated. In such a way, the bus master is separated in a second step, so that a bus cycle is not suddenly can celled.
JP23250187A 1987-09-18 1987-09-18 Bus adjusting device for multiplex input data transfer device Pending JPS6476256A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP23250187A JPS6476256A (en) 1987-09-18 1987-09-18 Bus adjusting device for multiplex input data transfer device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP23250187A JPS6476256A (en) 1987-09-18 1987-09-18 Bus adjusting device for multiplex input data transfer device

Publications (1)

Publication Number Publication Date
JPS6476256A true JPS6476256A (en) 1989-03-22

Family

ID=16940316

Family Applications (1)

Application Number Title Priority Date Filing Date
JP23250187A Pending JPS6476256A (en) 1987-09-18 1987-09-18 Bus adjusting device for multiplex input data transfer device

Country Status (1)

Country Link
JP (1) JPS6476256A (en)

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6863837B2 (en) * 2002-08-05 2005-03-08 Geo Specialty Chemicals, Inc. Dispersant composition
US7685473B2 (en) 2004-12-16 2010-03-23 Nec Corporation Computer system, method of detecting a stall in a computer system, and signal-bearing medium embodying a program causing a computer system to perform a method of detecting a stall in a computer system
JP2013544001A (en) * 2010-10-20 2013-12-09 クアルコム，インコーポレイテッド Arbitration of bus transactions on the communication bus and associated power management based on the health information of the bus device
JP2014081738A (en) * 2012-10-15 2014-05-08 Nagoya Univ Computer including bus partition structure

Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6863837B2 (en) * 2002-08-05 2005-03-08 Geo Specialty Chemicals, Inc. Dispersant composition
US7685473B2 (en) 2004-12-16 2010-03-23 Nec Corporation Computer system, method of detecting a stall in a computer system, and signal-bearing medium embodying a program causing a computer system to perform a method of detecting a stall in a computer system
JP2013544001A (en) * 2010-10-20 2013-12-09 クアルコム，インコーポレイテッド Arbitration of bus transactions on the communication bus and associated power management based on the health information of the bus device
US9064050B2 (en) 2010-10-20 2015-06-23 Qualcomm Incorporated Arbitrating bus transactions on a communications bus based on bus device health information and related power management
JP2014081738A (en) * 2012-10-15 2014-05-08 Nagoya Univ Computer including bus partition structure

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