JPS647567U - - Google Patents
Info
- Publication number
- JPS647567U JPS647567U JP10119287U JP10119287U JPS647567U JP S647567 U JPS647567 U JP S647567U JP 10119287 U JP10119287 U JP 10119287U JP 10119287 U JP10119287 U JP 10119287U JP S647567 U JPS647567 U JP S647567U
- Authority
- JP
- Japan
- Prior art keywords
- building
- sheet
- landscape
- base
- transparent
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 230000002093 peripheral effect Effects 0.000 claims description 5
- 238000010586 diagram Methods 0.000 description 7
Landscapes
- Floor Finish (AREA)
Description
図面はこの考案の実施例を示し、第１図は基台
の全体説明図、第２図ａ，ｂは建物シートの全体
説明図、第３図は玄関のイラストを描いた建築物
周辺部材シートの全体説明図、第４図は窓のイラ
ストを描いた建築物周辺部材シートの全体説明図
、第５図は外構部材のイラストを描いた建築物周
辺部材シートの全体説明図、第６図は前景を描い
た風景シートの全体説明図、第７図は第１図と第
２図を組合せた状態説明図、第８図は第７図に第
３図乃至第５図を組合せた状態説明図、第９図は
外観図の全体説明図。
１…建築物の外観図用イラストシート、２…背
景、３…基台、４…建築物、５…建物シート、６
…構成部材、７…外構部材、８…建築物周辺部材
シート、９…前景、１０…風景シート。
The drawings show an example of this invention. Fig. 1 is an overall explanatory diagram of the base, Fig. 2 a and b is an overall explanatory diagram of the building sheet, and Fig. 3 is a building peripheral material sheet with an illustration of the entrance. Figure 4 is an overall explanatory diagram of the building peripheral parts sheet with illustrations of windows, Figure 5 is an overall explanatory diagram of the building peripheral parts sheet with illustrations of external structural parts, and Figure 6 is an overall explanatory diagram of the landscape sheet depicting the foreground, Fig. 7 is an explanatory diagram of the state in which Figs. 1 and 2 are combined, and Fig. 8 is an explanatory diagram in which Fig. 7 is combined with Figs. 3 to 5. FIG. 9 is an overall explanatory view of the external appearance. 1... Illustration sheet for exterior drawing of building, 2... Background, 3... Base, 4... Building, 5... Building sheet, 6
... Component member, 7... External structure member, 8... Building peripheral member sheet, 9... Foreground, 10... Landscape sheet.
Claims (1)
合わせ可能な建築物を描いた建物シート、建築物
の構成部材や外構部材等を描いた透明の建築物周
辺部材シート、前景を描いた透明の風景シートと
の組合せからなることを特徴とする建築物の外観
図用イラストシート。 A base on which the background is depicted, a building sheet depicting a building that can be removably stacked on the base, a transparent building peripheral material sheet depicting building components and external structure members, etc., and a foreground. An illustration sheet for an exterior view of a building, characterized in that it is combined with a transparent landscape sheet depicting a landscape.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP10119287U JPS647567U (en) | 1987-06-30 | 1987-06-30 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP10119287U JPS647567U (en) | 1987-06-30 | 1987-06-30 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS647567U true JPS647567U (en) | 1989-01-17 |
Family
ID=31329962
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP10119287U Pending JPS647567U (en) | 1987-06-30 | 1987-06-30 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS647567U (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US7166503B2 (en) | 1993-10-01 | 2007-01-23 | Semiconductor Energy Laboratory Co., Ltd. | Method of manufacturing a TFT with laser irradiation |
| US7408233B2 (en) | 1993-01-18 | 2008-08-05 | Semiconductor Energy Laboratory Co., Ltd. | Semiconductor device having N-channel thin film transistor with LDD regions and P-channel thin film transistor with LDD region |
-
1987
- 1987-06-30 JP JP10119287U patent/JPS647567U/ja active Pending
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US7408233B2 (en) | 1993-01-18 | 2008-08-05 | Semiconductor Energy Laboratory Co., Ltd. | Semiconductor device having N-channel thin film transistor with LDD regions and P-channel thin film transistor with LDD region |
| US7166503B2 (en) | 1993-10-01 | 2007-01-23 | Semiconductor Energy Laboratory Co., Ltd. | Method of manufacturing a TFT with laser irradiation |