JPS6471229A - Phase lock system for subsequent synchronizing broadcast - Google Patents

Phase lock system for subsequent synchronizing broadcast

Info

Publication number
JPS6471229A
JPS6471229A JP62226296A JP22629687A JPS6471229A JP S6471229 A JPS6471229 A JP S6471229A JP 62226296 A JP62226296 A JP 62226296A JP 22629687 A JP22629687 A JP 22629687A JP S6471229 A JPS6471229 A JP S6471229A
Authority
JP
Japan
Prior art keywords
clear pulse
synchronizing signal
phase
scp
signal
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP62226296A
Other languages
Japanese (ja)
Inventor
Takashi Hanai
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp filed Critical NEC Corp
Priority to JP62226296A priority Critical patent/JPS6471229A/en
Publication of JPS6471229A publication Critical patent/JPS6471229A/en
Pending legal-status Critical Current

Links

Landscapes

  • Time-Division Multiplex Systems (AREA)
  • Synchronisation In Digital Transmission Systems (AREA)

Abstract

PURPOSE:To attain phase matching immediately even when the phase between broadcast stations is deviated by superimposing a clear pulse onto a synchronizing signal and allowing each broadcast station to match the phase of the synchronizing signal forcibly based on the clear pulse. CONSTITUTION:A synchronizing signal Sd of a signal generator 10 is given to an AM modulation section 24 and to a frequency division section 23 to form a clear pulse to always keep the phase of synchronization constant and a 100Hz clear pulse SCP is generated. The clear pulse SCP is given to the AM modulation section 24, superimposed on the synchronizing signal Sd and the result is sent to broadcast stations 20A', 20B', in which a multiple demodulation section 14 demultiplexes a synchronizing system signal Ss and an AM demodulation section 164 obtains the synchronizing signal Sd and the clear pulse SCP. Then the clear pulse SCP clears the frequency divider 15' forcibly to match the phase of the synchronizing signal Sd.
JP62226296A 1987-09-11 1987-09-11 Phase lock system for subsequent synchronizing broadcast Pending JPS6471229A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP62226296A JPS6471229A (en) 1987-09-11 1987-09-11 Phase lock system for subsequent synchronizing broadcast

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP62226296A JPS6471229A (en) 1987-09-11 1987-09-11 Phase lock system for subsequent synchronizing broadcast

Publications (1)

Publication Number Publication Date
JPS6471229A true JPS6471229A (en) 1989-03-16

Family

ID=16842986

Family Applications (1)

Application Number Title Priority Date Filing Date
JP62226296A Pending JPS6471229A (en) 1987-09-11 1987-09-11 Phase lock system for subsequent synchronizing broadcast

Country Status (1)

Country Link
JP (1) JPS6471229A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2009197915A (en) * 2008-02-21 2009-09-03 Aisin Ai Co Ltd Synchromesh mechanism of transmission
JP2016116038A (en) * 2014-12-12 2016-06-23 株式会社東芝 Transmitter and transmission method

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2009197915A (en) * 2008-02-21 2009-09-03 Aisin Ai Co Ltd Synchromesh mechanism of transmission
JP2016116038A (en) * 2014-12-12 2016-06-23 株式会社東芝 Transmitter and transmission method

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