JPS6467656A - Data assuring system - Google Patents

Data assuring system

Info

Publication number
JPS6467656A
JPS6467656A JP62225573A JP22557387A JPS6467656A JP S6467656 A JPS6467656 A JP S6467656A JP 62225573 A JP62225573 A JP 62225573A JP 22557387 A JP22557387 A JP 22557387A JP S6467656 A JPS6467656 A JP S6467656A
Authority
JP
Japan
Prior art keywords
data
area
binary addition
value
memory
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP62225573A
Other languages
Japanese (ja)
Inventor
Mitsuru Yoshida
Hiroaki Sakano
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Sharp Corp
Original Assignee
Sharp Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Sharp Corp filed Critical Sharp Corp
Priority to JP62225573A priority Critical patent/JPS6467656A/en
Publication of JPS6467656A publication Critical patent/JPS6467656A/en
Pending legal-status Critical Current

Links

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  • Techniques For Improving Reliability Of Storages (AREA)

Abstract

PURPOSE:To reduce memory capacity by storing the latest check sum data on subject data in a memory and comparing this check sum data with the binary addition value of the subject data. CONSTITUTION:The value obtained by applying binary addition to latest data in a data memory area is held by giving the binary addition or subtraction to the value of a check sum memory area 2 for each change of the data on a data memory area 1 and in accordance with said data change value. Then the binary addition is applied periodically to the data in the area 1 as necessary. The result of this binary addition is compared with the data stored in the area 2. Then the destruction of the data in the area 1 is decided and an alarm is produced in case no coincidence is obtained from said comparison. Thus it is possible to avoid a malfunction due to the use of the wrong data in a small capacity memory area with no data held overlapping with each other.
JP62225573A 1987-09-09 1987-09-09 Data assuring system Pending JPS6467656A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP62225573A JPS6467656A (en) 1987-09-09 1987-09-09 Data assuring system

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP62225573A JPS6467656A (en) 1987-09-09 1987-09-09 Data assuring system

Publications (1)

Publication Number Publication Date
JPS6467656A true JPS6467656A (en) 1989-03-14

Family

ID=16831424

Family Applications (1)

Application Number Title Priority Date Filing Date
JP62225573A Pending JPS6467656A (en) 1987-09-09 1987-09-09 Data assuring system

Country Status (1)

Country Link
JP (1) JPS6467656A (en)

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS52144235A (en) * 1976-05-27 1977-12-01 Toshiba Corp Breakdown detection system for memory capable of reading/writing
JPS5661096A (en) * 1979-10-22 1981-05-26 Fuji Electric Co Ltd Error detection system for read only memory electrically erasable
JPS58175199A (en) * 1982-04-07 1983-10-14 Fujitsu Ltd Memory check system

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS52144235A (en) * 1976-05-27 1977-12-01 Toshiba Corp Breakdown detection system for memory capable of reading/writing
JPS5661096A (en) * 1979-10-22 1981-05-26 Fuji Electric Co Ltd Error detection system for read only memory electrically erasable
JPS58175199A (en) * 1982-04-07 1983-10-14 Fujitsu Ltd Memory check system

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