JPS6465908A - Agc circuit - Google Patents
Agc circuitInfo
- Publication number
- JPS6465908A JPS6465908A JP22222487A JP22222487A JPS6465908A JP S6465908 A JPS6465908 A JP S6465908A JP 22222487 A JP22222487 A JP 22222487A JP 22222487 A JP22222487 A JP 22222487A JP S6465908 A JPS6465908 A JP S6465908A
- Authority
- JP
- Japan
- Prior art keywords
- bits
- alarm
- bit
- set value
- assumed
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Landscapes
- Control Of Amplification And Gain Control (AREA)
Abstract
PURPOSE:To prevent the influence of the variation of a lower order bit other than an alarm comparison bit upon alarm comparison even if said lower order bit always varies, and to obtain a stable operation by setting a set value in a comparator circuit 4 so as to set two bits, at least, of the highest order of the rest of the alarm comparison bit at '10' or '01'. CONSTITUTION:Among the set value of eight bits to be given to the comparator circuit 4, reference bits to generate an alarm are assumed to be the tour bits of the MSBs, and two bits other than those are assumed to be 01. Two bits of the further lower order are assumed to be 11, and all the four bits of the LSBs come to be 0111. In the case of this set value, even if the lowest order bit of the LSB side is increased by eight bits, it is not carried to the MSB side, and also, even if it is decreased by seven bits, it is not shifted down to the MSB side. Then, if the lowest order bit of the LSB side is increased by more than nine bits or is increased by more than eight bits, it is carried or shifted down, and since the alarm reference bit of a signal A changes, the input A and the set value B of the comparator circuit 4 come not equal to each other, and an alarm is generated.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP22222487A JPS6465908A (en) | 1987-09-04 | 1987-09-04 | Agc circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP22222487A JPS6465908A (en) | 1987-09-04 | 1987-09-04 | Agc circuit |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS6465908A true JPS6465908A (en) | 1989-03-13 |
Family
ID=16779065
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP22222487A Pending JPS6465908A (en) | 1987-09-04 | 1987-09-04 | Agc circuit |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS6465908A (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2005524325A (en) * | 2002-04-30 | 2005-08-11 | アドバンスト・マイクロ・ディバイシズ・インコーポレイテッド | Digital automatic gain control for transceivers |
-
1987
- 1987-09-04 JP JP22222487A patent/JPS6465908A/en active Pending
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2005524325A (en) * | 2002-04-30 | 2005-08-11 | アドバンスト・マイクロ・ディバイシズ・インコーポレイテッド | Digital automatic gain control for transceivers |
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