JPS645963Y2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a power-on circuit for a panel of an electronic device, and more particularly to a power-on circuit for a circuit that requires power-on sequencing.

Conventionally, the order in which electronic devices are turned on is determined by the operation of switches or relays.
In particular, a C-channel FET that operates with a positive power supply and an N-channel FET that operates with a negative power supply are connected in a complementary manner.
In the case of electronic devices that use integrated circuits with MOS logic circuits, when a panel is inserted or removed while the device is powered on, the latch-up of the C-MOS logic circuit may become unstable, causing momentary interruptions or malfunctions in other panels or channels. There are cases. This is because power is turned on out of order.

For this reason, a conventional circuit as shown in FIG. 1 has been used to determine the order in which power is turned on.

In Figure 1, 1 is the plug of the connector, 2 is the jack of the connector, 3 is the panel on which the C-MOS logic circuit is mounted, 4 is the contact (female) of the plug, 5-1, 5-2, 5- 3, 5-4 are jack contacts (male), and 5-1 is the voltage +
12V, -12V is used for 5-2, the potential of earth E is used for 5-3, and 5-4 is used for a signal power supply of +5V to be input to the C-MOS logic circuit. Reference numeral 6 indicates an electronic equipment power supply that supplies the necessary power to the C-MOS logic circuit.

Now, when connecting the panel 3 to the electronic device power supply 6 in the figure, the jack 2 of the panel 3 is inserted into the plug 1. In this case, the contacts (male) 5-1 to 4 of the jack 2 are connected to the contacts (female) of the plug 1. ) The order in which they are connected to 4 is 5-1, 5-2, 5-
This is done in the order of 3, 5-4.

In other words, the electric circuit on the panel side has +12V, -12V,
A potential is applied in the order of earth E and the input signal.

In this way, the ground E is connected as the final connection. The reason for this is that the potential connected to the panel is +
In the case of a normal plug-jack type where both 12V and ground are connected at the same time, when the jack contact (male) is connected to the plug contact (female), depending on the inclination at the time of insertion, the ground E, input This is because if the signal is connected first and the voltage ±12V is connected later, the circuit formed by the C-MOS IC will become unstable and may not operate normally. be. However, (1) if the number of stages in the ordering of the jacks is increased, the generality of the connector (plug-jack) will be lost. (2) As the number of sequences increases, the length of the jack contacts (male) inevitably becomes shorter, reducing the reliability of the contacts. Such disadvantages arise.

The present invention solves the above-mentioned drawbacks, has highly reliable contact, and solves the problem of C-
It provides a power-on circuit that supplies stable power to circuits such as MOS logic circuits.

Further, by using the n-step ordering by connectors (plugs and jacks), it is possible to perform power-on ordering in n+1 steps or more.

This will be explained in the embodiment shown in FIG.

In the figure, 11 is an electronic equipment power supply that supplies the power necessary for the C-MOS circuit, 12 is a plug, and 13
is the jack, 14 is the panel, 15-1, 15-2
is a contact (female) of the plug 12, 16 is a contact (male) of the plug 13, 17 is a potential generation circuit that generates a pseudo earth potential E, 18, 19 are Zener diodes, 20, 21 are resistors, 22, 2
3 and 24 are voltage terminals, 25 is a ground terminal, 22 is -12V, 23 is +12V, and 24 is +5V.

In FIG. 2, jack 13 is connected to plug 12 to connect panel 14 to electronic equipment power supply 11. In FIG. At this time, jack 13 contact (male)
16 is the plug contact (female) 15-
1, and then to a contact (female) 15-2 which is stepped from the contact 15-1. In this case, contact (male) 16 and contact (female)
When 15-1 is connected, the potential generation circuit 17 generates +12V - Resistor 20 - Zener diode 18 - Earth E・25 - Zener diode 19 - Resistor 21
--12V.22 current flows through the path, and a necessary pseudo earth potential E is generated at the connection point of the Zener diodes 18 and 19.

With the above circuit connections, the following operations are performed.

(1) ±12V is supplied to panel 14.

(2) A pseudo earth potential E is generated at the contact (male) 16-1 of the panel 14 and output to the earth terminal 25.

(3) The input signal +5V of the C-MOS logic circuit and the correct earth potential E are output.

As described above, power supply is performed in three stages in a two-stage contact order. In this case,
I used a zener diode, but the resistors 20 and 21
It's fine just by itself.

[Brief explanation of the drawing]

FIG. 1 is a conventional diagram, and FIG. 2 is a diagram showing an embodiment of the present invention. In the figure, 1...plug, 2...jack,
4... Contact (female), 5-1, 5-2, 5
-3,5-4...Contact (male), 15-1,
15-2... Contact (female), 16... Contact (male), 17... Potential generation circuit, 20,
21... shows resistance.

Claims (1)

[Scope of utility model registration request] A power supply circuit for a circuit that requires the order in which a plurality of power supplies are supplied is equipped with a potential generation circuit 17 that pseudo-generates the potential that should be supplied next from the first supply supply, and is used to supply a plurality of power supplies. A power-on circuit characterized by reducing the number of stages.