JPS6459415A - Multiplexing interface control circuit - Google Patents

Multiplexing interface control circuit

Info

Publication number
JPS6459415A
JPS6459415A JP21612687A JP21612687A JPS6459415A JP S6459415 A JPS6459415 A JP S6459415A JP 21612687 A JP21612687 A JP 21612687A JP 21612687 A JP21612687 A JP 21612687A JP S6459415 A JPS6459415 A JP S6459415A
Authority
JP
Japan
Prior art keywords
interface control
circuit
clock
interface
control circuits
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP21612687A
Other languages
Japanese (ja)
Inventor
Satoshi Nagasaki
Osamu Suzuki
Toshihiro Hamada
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
PFU Ltd
Original Assignee
Fujitsu Ltd
PFU Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd, PFU Ltd filed Critical Fujitsu Ltd
Priority to JP21612687A priority Critical patent/JPS6459415A/en
Publication of JPS6459415A publication Critical patent/JPS6459415A/en
Pending legal-status Critical Current

Links

Abstract

PURPOSE:To optimumly hold the efficiency of a circuit of a device connected by only selecting an interface circuit, by providing plural interface control circuit which are multiplexed. CONSTITUTION:The output from an internal circuit 11 is outputted to a common bus through plural interface control circuits 121-12n which are fractionated to an optimum speed corresponding to the kind of a connecting device. Subsequently, these interface control circuits 121-12n are selected by putting the set information into a selector 13. As for a fundamental clock for operating the interface control circuits 121-12n in this case, there are that which is supplied a clock 14 for controlling the whole system from the outside, and that which is supplied the clock 14 from an internal clock generating part 15. This selection is executed by both transmitting and receiving sides and connected. In such a way, in an operating speed of both interface circuits, the most satisfactory operation efficiency is obtained.
JP21612687A 1987-08-29 1987-08-29 Multiplexing interface control circuit Pending JPS6459415A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP21612687A JPS6459415A (en) 1987-08-29 1987-08-29 Multiplexing interface control circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP21612687A JPS6459415A (en) 1987-08-29 1987-08-29 Multiplexing interface control circuit

Publications (1)

Publication Number Publication Date
JPS6459415A true JPS6459415A (en) 1989-03-07

Family

ID=16683666

Family Applications (1)

Application Number Title Priority Date Filing Date
JP21612687A Pending JPS6459415A (en) 1987-08-29 1987-08-29 Multiplexing interface control circuit

Country Status (1)

Country Link
JP (1) JPS6459415A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO1991016676A1 (en) * 1990-04-17 1991-10-31 Seiko Epson Corporation Personal computer
JP2008040873A (en) * 2006-08-08 2008-02-21 Ricoh Co Ltd Data speed conversion integrated circuit and image forming apparatus

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO1991016676A1 (en) * 1990-04-17 1991-10-31 Seiko Epson Corporation Personal computer
JP2008040873A (en) * 2006-08-08 2008-02-21 Ricoh Co Ltd Data speed conversion integrated circuit and image forming apparatus

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