JPS6457550U - - Google Patents
Info
- Publication number
- JPS6457550U JPS6457550U JP1987153010U JP15301087U JPS6457550U JP S6457550 U JPS6457550 U JP S6457550U JP 1987153010 U JP1987153010 U JP 1987153010U JP 15301087 U JP15301087 U JP 15301087U JP S6457550 U JPS6457550 U JP S6457550U
- Authority
- JP
- Japan
- Prior art keywords
- receiving elements
- light receiving
- signal processing
- processing circuit
- logic array
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000000034 method Methods 0.000 claims 1
- 238000010586 diagram Methods 0.000 description 5
Landscapes
- Image Processing (AREA)
- Transforming Light Signals Into Electric Signals (AREA)
Description
第１図は、この考案のロジツクアレイの構成ブ
ロツク図である。第２図は、静止画像の輪郭を認
識する信号処理回路を示した回路ブロツク図であ
る。第３図は、その出力例を示した概念図である
。第４図は、動画像の輪郭を認識する信号処理回
路を示した回路ブロツク図である。第５図はその
出力例を示した概念図である。
１……受光素子、２……信号処理回路、３……
データ・エンコーダ、１ａ，１ｂ……受光素子、
４……アンプ／レベルシフタ、５……ＸＯＲゲー
ト、６……輪郭線、７……バツフアアンプ、８…
…遅延回路、９……ＸＯＲロジツク、Ａ……カラ
ム・アドレス、Ｂ……ロワ・アドレス、Ｃ……出
力、Ｄ……出力、Ｅ……出力。
FIG. 1 is a block diagram of the configuration of the logic array of this invention. FIG. 2 is a circuit block diagram showing a signal processing circuit for recognizing the outline of a still image. FIG. 3 is a conceptual diagram showing an example of the output. FIG. 4 is a circuit block diagram showing a signal processing circuit for recognizing the outline of a moving image. FIG. 5 is a conceptual diagram showing an example of the output. 1... Light receiving element, 2... Signal processing circuit, 3...
Data encoder, 1a, 1b...light receiving element,
4...Amplifier/level shifter, 5...XOR gate, 6...Contour line, 7...Buffer amplifier, 8...
...Delay circuit, 9...XOR logic, A...Column address, B...Lower address, C...Output, D...Output, E...Output.
Claims (1)
信号処理を個別に行う信号処理回路とを有し、信
号処理回路を全ての受光素子の周辺に配置してな
ることを特徴とするロジツクアレイ。 (2) 隣接する受光素子の出力の排他的論理和を
とるためのロジツク回路を設け、静止画像の輪郭
を認識する実用新案登録請求の範囲第(1)項記載
のロジツクアレイ。 (3) 隣接する受光素子の出力を分岐し、遅延回
路を通した一方の出力と直接の出力との排他的論
理和をとる信号処理回路を設け、動画像の輪郭を
認識する実用新案登録請求の範囲第(1)項記載の
ロジツクアレイ。[Claims for Utility Model Registration] (1) A device that has a plurality of arrayed light receiving elements and a signal processing circuit that individually processes the signals of the light receiving elements, and the signal processing circuit is arranged around all the light receiving elements. A logic array that is characterized by (2) The logic array according to claim (1), which is provided with a logic circuit for taking the exclusive OR of the outputs of adjacent light receiving elements and recognizes the outline of a still image. (3) Request for utility model registration to recognize the outline of a moving image by installing a signal processing circuit that branches the outputs of adjacent light-receiving elements and performs an exclusive OR of one output through a delay circuit and the direct output. The logic array described in scope (1).
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1987153010U JPS6457550U (en) | 1987-10-06 | 1987-10-06 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1987153010U JPS6457550U (en) | 1987-10-06 | 1987-10-06 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS6457550U true JPS6457550U (en) | 1989-04-10 |
Family
ID=31428461
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP1987153010U Pending JPS6457550U (en) | 1987-10-06 | 1987-10-06 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS6457550U (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2003023712A1 (en) * | 2001-09-05 | 2003-03-20 | Japan Science And Technology Agency | Image sensing apparatus |
-
1987
- 1987-10-06 JP JP1987153010U patent/JPS6457550U/ja active Pending
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2003023712A1 (en) * | 2001-09-05 | 2003-03-20 | Japan Science And Technology Agency | Image sensing apparatus |
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