JPS6455986A - Video signal sampling device - Google Patents

Abstract

PURPOSE:To reduce shift of a sampling clock at low cost by generating plural kinds of clocks whose phases are shifted from each other, and selecting a clock that rises earliest after the ending of a horizontal synchronizing signal separated by a synchronizing separating circuit. CONSTITUTION:A clock generating circuit generates plural kinds of clocks in the same frequency whose phases are shifted from each other. When a horizontal synchronizing signal HSC is inputted respectively to the clear terminals CLRs of D-flip-flops D-FF0-D-FF7, the D-flip-flops D-FF0-D-FF7 are released from the clear-state after the lapse of a delay time t0. After the rising of the earliest clock LCK0 following this releasing, a disabling signal DISABLE comes in a high level after the lapse of a delay time t1 possessed by the D-flip-flop D-FF0 and an eight-input NOR gate NOR. Accordingly, in this status, only a selection signal SEL0 comes in a high level, hence a clock CLK0 is selected as a sampling clock and supplied to an A/D converter 4 during one horizontal period.