JPS6454411A - Synchronizing signal generating method - Google Patents

Synchronizing signal generating method

Info

Publication number
JPS6454411A
JPS6454411A JP62210654A JP21065487A JPS6454411A JP S6454411 A JPS6454411 A JP S6454411A JP 62210654 A JP62210654 A JP 62210654A JP 21065487 A JP21065487 A JP 21065487A JP S6454411 A JPS6454411 A JP S6454411A
Authority
JP
Japan
Prior art keywords
signal
circuit
inputted
synchronizing signal
image
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP62210654A
Other languages
Japanese (ja)
Inventor
Akira Yamaguchi
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujifilm Holdings Corp
Original Assignee
Fuji Photo Film Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fuji Photo Film Co Ltd filed Critical Fuji Photo Film Co Ltd
Priority to JP62210654A priority Critical patent/JPS6454411A/en
Publication of JPS6454411A publication Critical patent/JPS6454411A/en
Pending legal-status Critical Current

Links

Abstract

PURPOSE:To simplify the structure and reduce the size by smoothing a speed signal obtained by differentiating a position signal from an optical deflector, then performing voltage-frequency conversion and multiplication, and using the resulting signal as a synchronizing signal for reading or recording an image, etc. CONSTITUTION:The position signal P from a position sensor incorporated in a galvanometer mirror 10 is inputted to a differentiating circuit 34. The output signal of the differentiating circuit 34 is inputted to an N-multiplying PLL (NPLL) circuit 38 through a voltage-frequency (V/F) converting circuit 36 and the output signal of the NPLL circuit 38 is inputted to the 1st synchronizing signal input terminal of an A/D converting circuit 46 as the synchronizing signal. The output signal of a comparing circuit 50, on the other hand, is inputted as a start point control signal 52 to the 2nd synchronizing signal input terminal of the A/D converting circuit 46. Then the output signal of the A/D converting circuit 46 is image-processed at need and then inputted to an image reproducing device such as a CRT and a laser printer to reproduce a visual image. Consequently, the constitution is simplified and reduced in size.
JP62210654A 1987-08-24 1987-08-24 Synchronizing signal generating method Pending JPS6454411A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP62210654A JPS6454411A (en) 1987-08-24 1987-08-24 Synchronizing signal generating method

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP62210654A JPS6454411A (en) 1987-08-24 1987-08-24 Synchronizing signal generating method

Publications (1)

Publication Number Publication Date
JPS6454411A true JPS6454411A (en) 1989-03-01

Family

ID=16592889

Family Applications (1)

Application Number Title Priority Date Filing Date
JP62210654A Pending JPS6454411A (en) 1987-08-24 1987-08-24 Synchronizing signal generating method

Country Status (1)

Country Link
JP (1) JPS6454411A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE19806664C1 (en) * 1998-02-18 1999-04-08 Fraunhofer Ges Forschung Image spot clock generator for digital exposure device

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE19806664C1 (en) * 1998-02-18 1999-04-08 Fraunhofer Ges Forschung Image spot clock generator for digital exposure device

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