JPS6453496A - Formation of wiring - Google Patents

Formation of wiring

Info

Publication number
JPS6453496A
JPS6453496A JP20989587A JP20989587A JPS6453496A JP S6453496 A JPS6453496 A JP S6453496A JP 20989587 A JP20989587 A JP 20989587A JP 20989587 A JP20989587 A JP 20989587A JP S6453496 A JPS6453496 A JP S6453496A
Authority
JP
Japan
Prior art keywords
layer wiring
conducting current
conductor
electrolysis plating
etching
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP20989587A
Other languages
Japanese (ja)
Inventor
Wataru Fujisawa
Katsuhiko Oguri
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Victor Company of Japan Ltd
Original Assignee
Victor Company of Japan Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Victor Company of Japan Ltd filed Critical Victor Company of Japan Ltd
Priority to JP20989587A priority Critical patent/JPS6453496A/en
Publication of JPS6453496A publication Critical patent/JPS6453496A/en
Pending legal-status Critical Current

Links

Landscapes

  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Production Of Multi-Layered Print Wiring Board (AREA)

Abstract

PURPOSE:A lower-layer wiring for conducting current is cut without damaging a substrate by removing one part of the lower-layer wiring for conducting current by etching after burying a contact hole with conductor by performing electrolysis plating using a lower-layer wiring for conducting current. CONSTITUTION:A lower-layer wiring 11, lower-layer wiring for conducting current 11a, and common electrode 11b for electrolysis plating are formed on a flat-plate substrate 10 by a thin-film formation means. A conductor 13 which can be easily eliminated by etching is formed between the lower-layer wiring 11 and the lower-layer wiring 11a for conducting current to connect both in terms of electricity. After a contact hole 16 is formed, voltage is applied to the common electrode 11b for electrolysis plating and electrically is applied to the lower-layer wiring 11 and lower-layer wiring 11a for conducting current, and a contact hole 16 is buried with a conductor 17 by electrolysis plating. After an upper-layer wiring 19 is formed, a conductor 13 is removed by etching through a hole 12 and the lower-layer wiring 11 and lower-layer wiring 11a for conducting current are disconnected electrically.
JP20989587A 1987-08-24 1987-08-24 Formation of wiring Pending JPS6453496A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP20989587A JPS6453496A (en) 1987-08-24 1987-08-24 Formation of wiring

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP20989587A JPS6453496A (en) 1987-08-24 1987-08-24 Formation of wiring

Publications (1)

Publication Number Publication Date
JPS6453496A true JPS6453496A (en) 1989-03-01

Family

ID=16580422

Family Applications (1)

Application Number Title Priority Date Filing Date
JP20989587A Pending JPS6453496A (en) 1987-08-24 1987-08-24 Formation of wiring

Country Status (1)

Country Link
JP (1) JPS6453496A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0360188A (en) * 1989-07-27 1991-03-15 Bull Sa Method of forming multilayer wiring network of connection board with high density integrated circuit
JPH03296222A (en) * 1990-04-13 1991-12-26 Nec Corp Semiconductor device and its manufacture

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0360188A (en) * 1989-07-27 1991-03-15 Bull Sa Method of forming multilayer wiring network of connection board with high density integrated circuit
JPH03296222A (en) * 1990-04-13 1991-12-26 Nec Corp Semiconductor device and its manufacture

Similar Documents

Publication Publication Date Title
IL111308A (en) Multi-level antifuse structure and method for making same
TW344888B (en) Electroplated solder terminal
EP0879470A4 (en) Over-voltage protection device and method for making same
JPS6471147A (en) Solid state circuit with laser-fusible link
DE58907877D1 (en) Method for automatically mounting electrical conductors with contact parts in connector housings.
AU2002336089A1 (en) Segmented counterelectrode for an electrolytic treatment system
EP0372930A3 (en) Electrolytic etch for preventing electrical shorts in solar cells on polymer surfaces
EP0218437A3 (en) A microelectronics apparatus and method of interconnecting wiring planes
EP0394722A3 (en) Multilevel metallization for vlsi and method for forming the same
EP0735623A3 (en) Electrical connector
MY120508A (en) Electrical connector.
JPS6453496A (en) Formation of wiring
DE3669812D1 (en) CONNECTOR WITH OPTIONAL INTERNAL ELECTRICAL CONNECTIONS.
EP0388341A3 (en) Method and apparatus for causing an open circuit in a conductive line
EP0213046A3 (en) Electronic card connecting circuit
ES466953A1 (en) Connector for electrical components to be installed in flush receptacle boxes
HK103693A (en) Integrated circuit with an electroconductive flat element
JPS6448423A (en) Dividing method of semiconductor chip
EP0312607A4 (en) Power circuit board and manufacturing method
EP0190855A3 (en) Improved photovoltaic device tolerant of low resistance defects
ES2179062T3 (en) COMPACT CONNECTOR, AND SHIELDED FOR DATA TRANSMISSION.
JPH067576Y2 (en) Terminal block
TW370716B (en) Structure and method for manufacturing interconnects
JPS6411349A (en) Semiconductor device
CA2020089A1 (en) Method and construction of electrical connection to oxide superconductor