JPS6453496A - Formation of wiring - Google Patents
Formation of wiringInfo
- Publication number
- JPS6453496A JPS6453496A JP20989587A JP20989587A JPS6453496A JP S6453496 A JPS6453496 A JP S6453496A JP 20989587 A JP20989587 A JP 20989587A JP 20989587 A JP20989587 A JP 20989587A JP S6453496 A JPS6453496 A JP S6453496A
- Authority
- JP
- Japan
- Prior art keywords
- layer wiring
- conducting current
- conductor
- electrolysis plating
- etching
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Landscapes
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
- Production Of Multi-Layered Print Wiring Board (AREA)
Abstract
PURPOSE:A lower-layer wiring for conducting current is cut without damaging a substrate by removing one part of the lower-layer wiring for conducting current by etching after burying a contact hole with conductor by performing electrolysis plating using a lower-layer wiring for conducting current. CONSTITUTION:A lower-layer wiring 11, lower-layer wiring for conducting current 11a, and common electrode 11b for electrolysis plating are formed on a flat-plate substrate 10 by a thin-film formation means. A conductor 13 which can be easily eliminated by etching is formed between the lower-layer wiring 11 and the lower-layer wiring 11a for conducting current to connect both in terms of electricity. After a contact hole 16 is formed, voltage is applied to the common electrode 11b for electrolysis plating and electrically is applied to the lower-layer wiring 11 and lower-layer wiring 11a for conducting current, and a contact hole 16 is buried with a conductor 17 by electrolysis plating. After an upper-layer wiring 19 is formed, a conductor 13 is removed by etching through a hole 12 and the lower-layer wiring 11 and lower-layer wiring 11a for conducting current are disconnected electrically.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP20989587A JPS6453496A (en) | 1987-08-24 | 1987-08-24 | Formation of wiring |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP20989587A JPS6453496A (en) | 1987-08-24 | 1987-08-24 | Formation of wiring |
Publications (1)
Publication Number | Publication Date |
---|---|
JPS6453496A true JPS6453496A (en) | 1989-03-01 |
Family
ID=16580422
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP20989587A Pending JPS6453496A (en) | 1987-08-24 | 1987-08-24 | Formation of wiring |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS6453496A (en) |
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH0360188A (en) * | 1989-07-27 | 1991-03-15 | Bull Sa | Method of forming multilayer wiring network of connection board with high density integrated circuit |
JPH03296222A (en) * | 1990-04-13 | 1991-12-26 | Nec Corp | Semiconductor device and its manufacture |
-
1987
- 1987-08-24 JP JP20989587A patent/JPS6453496A/en active Pending
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH0360188A (en) * | 1989-07-27 | 1991-03-15 | Bull Sa | Method of forming multilayer wiring network of connection board with high density integrated circuit |
JPH03296222A (en) * | 1990-04-13 | 1991-12-26 | Nec Corp | Semiconductor device and its manufacture |
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