JPS6452323U - - Google Patents

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Publication number
JPS6452323U
JPS6452323U JP14778187U JP14778187U JPS6452323U JP S6452323 U JPS6452323 U JP S6452323U JP 14778187 U JP14778187 U JP 14778187U JP 14778187 U JP14778187 U JP 14778187U JP S6452323 U JPS6452323 U JP S6452323U
Authority
JP
Japan
Prior art keywords
delay circuit
power
power amplifiers
transmitter
cascaded
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP14778187U
Other languages
Japanese (ja)
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed filed Critical
Priority to JP14778187U priority Critical patent/JPS6452323U/ja
Publication of JPS6452323U publication Critical patent/JPS6452323U/ja
Pending legal-status Critical Current

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Description

【図面の簡単な説明】[Brief explanation of the drawing]

第1図はこの考案の一実施例による送信装置の
増幅部を示すブロツク図、第2図は第1図の一部
の詳細図、第3図は従来の送信装置の増幅部を示
すブロツク図、第4図は他の実施例による送信装
置を示すブロツク図、第5図は出力等価回路を示
す図である。 図において、1〜3は増幅器、4は電源スイツ
チ、5は遅延回路、6はパワートランジスタ、7
は自動電力制御用回路、8はカプラー、51は他
の実施例による遅延回路である。なお、図中、同
一符号は同一、又は相当部分を示す。
FIG. 1 is a block diagram showing an amplifying section of a transmitting device according to an embodiment of this invention, FIG. 2 is a detailed view of a part of FIG. 1, and FIG. 3 is a block diagram showing an amplifying section of a conventional transmitting device. , FIG. 4 is a block diagram showing a transmitter according to another embodiment, and FIG. 5 is a diagram showing an output equivalent circuit. In the figure, 1 to 3 are amplifiers, 4 is a power switch, 5 is a delay circuit, 6 is a power transistor, and 7 is a power switch.
8 is a coupler, and 51 is a delay circuit according to another embodiment. In addition, in the figures, the same reference numerals indicate the same or equivalent parts.

Claims (1)

【実用新案登録請求の範囲】[Scope of utility model registration request] 縦続接続された複数の送信用の電力増幅器と、
この複数の電力増幅器の初段の電源供給ラインに
挿入された遅延回路とを備え、電源を遅延回路を
経て供給することによりラツシユ電流を軽減する
ようにしたことを特徴とする送信装置。
a plurality of cascaded transmitting power amplifiers;
A transmitter comprising: a delay circuit inserted into a power supply line of the first stage of the plurality of power amplifiers; and supplying power through the delay circuit to reduce rush current.
JP14778187U 1987-09-28 1987-09-28 Pending JPS6452323U (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP14778187U JPS6452323U (en) 1987-09-28 1987-09-28

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP14778187U JPS6452323U (en) 1987-09-28 1987-09-28

Publications (1)

Publication Number Publication Date
JPS6452323U true JPS6452323U (en) 1989-03-31

Family

ID=31418501

Family Applications (1)

Application Number Title Priority Date Filing Date
JP14778187U Pending JPS6452323U (en) 1987-09-28 1987-09-28

Country Status (1)

Country Link
JP (1) JPS6452323U (en)

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