JPS6452065U - - Google Patents

Info

Publication number
JPS6452065U
JPS6452065U JP14497287U JP14497287U JPS6452065U JP S6452065 U JPS6452065 U JP S6452065U JP 14497287 U JP14497287 U JP 14497287U JP 14497287 U JP14497287 U JP 14497287U JP S6452065 U JPS6452065 U JP S6452065U
Authority
JP
Japan
Prior art keywords
input
output interface
read request
driver
terminal device
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP14497287U
Other languages
Japanese (ja)
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed filed Critical
Priority to JP14497287U priority Critical patent/JPS6452065U/ja
Publication of JPS6452065U publication Critical patent/JPS6452065U/ja
Pending legal-status Critical Current

Links

Description

【図面の簡単な説明】[Brief explanation of the drawing]

第１図は本考案を実施した入出力インターフエ
イス・ドライバ３を用いたシステムを表わす図、
第２図は本考案に用いるインターフエイス・カー
ド２の構成図、第３図ａ，ｂは送受信テキストと
通信要求情報のタイミングを表わす図である。 １……端末機器、２……インターフエイス・カ
ード、２１……ＵＡＲＴ、２１１……受信バツフ
ア、２１２……直並列変換回路、２１３……送信
バツフア、２１４……並直列変換回路、２２……
ＤＭＡ回路、２３……制御回路、ｒ……レシーバ
、ｄ……ドライバ、３……インターフエイス・ド
ライバ、４……ターミナル・デバイス・ドライバ
、５……アプリケーシヨン・プログラム。 FIG. 1 is a diagram showing a system using an input/output interface driver 3 implementing the present invention.
FIG. 2 is a block diagram of the interface card 2 used in the present invention, and FIGS. 3a and 3b are diagrams showing the timing of transmitted/received text and communication request information. DESCRIPTION OF SYMBOLS 1...Terminal equipment, 2...Interface card, 21...UART, 211...Receiving buffer, 212...Serial-to-parallel conversion circuit, 213...Transmission buffer, 214...Parallel-serial conversion circuit, 22...
DMA circuit, 23...control circuit, r...receiver, d...driver, 3...interface driver, 4...terminal device driver, 5...application program.

Claims (1)

【実用新案登録請求の範囲】[Scope of utility model registration request] 計算機システムと端末機器等とを半二重通信方
式で接続する入出力インターフエイスの動作を制
御する入出力インターフエイス・ドライバにおい
て、リード要求が与えられていないときに入力さ
れた前記端末機器側からの１文字分の通信要求情
報を次のリード要求があるまで保持する手段を設
けたことを特徴とする入出力インターフエイス・
ドライバ。 In an input/output interface driver that controls the operation of an input/output interface that connects a computer system and a terminal device, etc. using a half-duplex communication method, a read request is input from the terminal device side when no read request is given. An input/output interface characterized by providing means for holding communication request information for one character until the next read request.
driver.
JP14497287U 1987-09-22 1987-09-22 Pending JPS6452065U (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP14497287U JPS6452065U (en) 1987-09-22 1987-09-22

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP14497287U JPS6452065U (en) 1987-09-22 1987-09-22

Publications (1)

Publication Number Publication Date
JPS6452065U true JPS6452065U (en) 1989-03-30

Family

ID=31413151

Family Applications (1)

Application Number Title Priority Date Filing Date
JP14497287U Pending JPS6452065U (en) 1987-09-22 1987-09-22

Country Status (1)

Country Link
JP (1) JPS6452065U (en)

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS61250758A (en) * 1985-04-30 1986-11-07 Toshiba Corp Communication controller
JPS61251252A (en) * 1985-04-30 1986-11-08 Hitachi Ltd Processing method for data transfer

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS61250758A (en) * 1985-04-30 1986-11-07 Toshiba Corp Communication controller
JPS61251252A (en) * 1985-04-30 1986-11-08 Hitachi Ltd Processing method for data transfer

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