JPS6451808A - Differential amplifier device - Google Patents

Differential amplifier device

Info

Publication number
JPS6451808A
JPS6451808A JP62209678A JP20967887A JPS6451808A JP S6451808 A JPS6451808 A JP S6451808A JP 62209678 A JP62209678 A JP 62209678A JP 20967887 A JP20967887 A JP 20967887A JP S6451808 A JPS6451808 A JP S6451808A
Authority
JP
Japan
Prior art keywords
output
input
current mirror
differential amplifier
mirror circuit
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP62209678A
Other languages
Japanese (ja)
Inventor
Tetsuro Nagahisa
Yuji Tanaka
Hidetoshi Imai
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Panasonic Holdings Corp
Original Assignee
Matsushita Electric Industrial Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Matsushita Electric Industrial Co Ltd filed Critical Matsushita Electric Industrial Co Ltd
Priority to JP62209678A priority Critical patent/JPS6451808A/en
Publication of JPS6451808A publication Critical patent/JPS6451808A/en
Pending legal-status Critical Current

Links

Abstract

PURPOSE:To stabilize the output by increasing/decreasing one input as soon as an output transistor(TR) is turned off from ON or vice versa. CONSTITUTION:The input/output of a 1st current mirror circuit 6 is connected to the output of a differential amplifier 3, the base of a 1st TR 1 is connected to one output of the differential amplifier 3, the power supply of a 2nd current mirror circuit 13 is connected to the collector of the 1st TR 1 and one input of the differential amplifier 3 and the resistor 14 are connected to the input of the 2nd current mirror circuit 13 to keep the other terminal of the resistor 14 to a fixed potential and the output of the 2nd current mirror 13 to make the output of the 2nd current mirror 13 as the circuit output I0. When an inverted level has a width while the 1st TR 1 is turned from ON to OFF or vice versa and even if the input comparison level has a minute change, the 1st TR 1 keeps the preceding state. Thus, the stable output is attained.
JP62209678A 1987-08-24 1987-08-24 Differential amplifier device Pending JPS6451808A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP62209678A JPS6451808A (en) 1987-08-24 1987-08-24 Differential amplifier device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP62209678A JPS6451808A (en) 1987-08-24 1987-08-24 Differential amplifier device

Publications (1)

Publication Number Publication Date
JPS6451808A true JPS6451808A (en) 1989-02-28

Family

ID=16576802

Family Applications (1)

Application Number Title Priority Date Filing Date
JP62209678A Pending JPS6451808A (en) 1987-08-24 1987-08-24 Differential amplifier device

Country Status (1)

Country Link
JP (1) JPS6451808A (en)

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5979628A (en) * 1982-10-28 1984-05-08 Matsushita Electric Ind Co Ltd Comparator

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5979628A (en) * 1982-10-28 1984-05-08 Matsushita Electric Ind Co Ltd Comparator

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