JPS6451332U - - Google Patents
Info
- Publication number
- JPS6451332U JPS6451332U JP14613687U JP14613687U JPS6451332U JP S6451332 U JPS6451332 U JP S6451332U JP 14613687 U JP14613687 U JP 14613687U JP 14613687 U JP14613687 U JP 14613687U JP S6451332 U JPS6451332 U JP S6451332U
- Authority
- JP
- Japan
- Prior art keywords
- prescaler
- local oscillation
- circuit
- input
- utility
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 230000010355 oscillation Effects 0.000 claims description 3
- 239000003990 capacitor Substances 0.000 description 2
- 238000010586 diagram Methods 0.000 description 2
- 230000008878 coupling Effects 0.000 description 1
- 238000010168 coupling process Methods 0.000 description 1
- 238000005859 coupling reaction Methods 0.000 description 1
Landscapes
- Electronic Switches (AREA)
- Stabilization Of Oscillater, Synchronisation, Frequency Synthesizers (AREA)
- Superheterodyne Receivers (AREA)
Description
第１図は本考案によるプリスケーラ入力回路の
回路図、第２図はＰＬＬ受信機の基本構成を示す
図である。
１３……ＦＭフロントエンド、１４……アンテ
ナ入力、１５……局部発振出力、１６……プリス
ケーラ入力に至る端子、Ｑ１……ＮＰＮトランジ
スタ、Ｃ１，Ｃ３……結合コンデンサ、Ｃ２……
バイパスコンデンサ、Ｒ１，Ｒ２，Ｒ３……バイ
アス抵抗、Ｌ……負荷リアクタンス、ＳＧ……強
信号下のアンテナ。
FIG. 1 is a circuit diagram of a prescaler input circuit according to the present invention, and FIG. 2 is a diagram showing the basic configuration of a PLL receiver. 13...FM front end, 14...Antenna input, 15...Local oscillation output, 16...Terminal leading to prescaler input, Q1 ...NPN transistor, C1 , C3 ...Coupling capacitor, C2 ...
Bypass capacitor, R1 , R2 , R3 ...Bias resistance, L...Load reactance, SG...Antenna under strong signal.
Claims (1)
路中のプリスケーラの入力端の間に設けられた、
フロントエンド側のインピーダンスを低下させる
増幅回路 を含むことを特徴とするプリスケーラ入力回路。[Claims for Utility Model Registration] Provided between the local oscillation output terminal of the front end and the input terminal of the prescaler in the local oscillation circuit,
A prescaler input circuit characterized by including an amplifier circuit that reduces impedance on the front end side.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP14613687U JPS6451332U (en) | 1987-09-25 | 1987-09-25 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP14613687U JPS6451332U (en) | 1987-09-25 | 1987-09-25 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS6451332U true JPS6451332U (en) | 1989-03-30 |
Family
ID=31415343
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP14613687U Pending JPS6451332U (en) | 1987-09-25 | 1987-09-25 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS6451332U (en) |
-
1987
- 1987-09-25 JP JP14613687U patent/JPS6451332U/ja active Pending
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