JPS6450051A - Rom mask pattern setting method - Google Patents

Rom mask pattern setting method

Info

Publication number
JPS6450051A
JPS6450051A JP20652387A JP20652387A JPS6450051A JP S6450051 A JPS6450051 A JP S6450051A JP 20652387 A JP20652387 A JP 20652387A JP 20652387 A JP20652387 A JP 20652387A JP S6450051 A JPS6450051 A JP S6450051A
Authority
JP
Japan
Prior art keywords
mask pattern
rom
pattern setting
arrangement rule
information
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP20652387A
Other languages
Japanese (ja)
Inventor
Atsushi Nagashima
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Panasonic Holdings Corp
Original Assignee
Matsushita Electronics Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Matsushita Electronics Corp filed Critical Matsushita Electronics Corp
Priority to JP20652387A priority Critical patent/JPS6450051A/en
Publication of JPS6450051A publication Critical patent/JPS6450051A/en
Pending legal-status Critical Current

Links

Landscapes

  • Exposure Of Semiconductors, Excluding Electron Or Ion Beam Exposure (AREA)
  • Design And Manufacture Of Integrated Circuits (AREA)
  • Semiconductor Memories (AREA)
  • Preparing Plates And Mask In Photomechanical Process (AREA)
  • Read Only Memory (AREA)

Abstract

PURPOSE:To improve operation efficiency by setting the arrangement of a mask pattern according to a ROM information arrangement rule stored in the storage device of a computer previously. CONSTITUTION:Data wherein arrangement rule information for the ROM mask pattern setting is determined is generated and stored in the storage device of the computer previously. A program for the ROM mask pattern setting is executed according to said data and information offered through a medium. There is only one program for the ROM mask pattern setting and when the design specification of a ROM part is different or changed, the arrangement rule information is only generated or modified. This arrangement rule information data is generated relatively easily. Consequently, the operation efficiency is improved.
JP20652387A 1987-08-21 1987-08-21 Rom mask pattern setting method Pending JPS6450051A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP20652387A JPS6450051A (en) 1987-08-21 1987-08-21 Rom mask pattern setting method

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP20652387A JPS6450051A (en) 1987-08-21 1987-08-21 Rom mask pattern setting method

Publications (1)

Publication Number Publication Date
JPS6450051A true JPS6450051A (en) 1989-02-27

Family

ID=16524776

Family Applications (1)

Application Number Title Priority Date Filing Date
JP20652387A Pending JPS6450051A (en) 1987-08-21 1987-08-21 Rom mask pattern setting method

Country Status (1)

Country Link
JP (1) JPS6450051A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8808061B2 (en) 2010-06-21 2014-08-19 Fujikoshi Machinery Corp. Method and apparatus for dressing polishing pad

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8808061B2 (en) 2010-06-21 2014-08-19 Fujikoshi Machinery Corp. Method and apparatus for dressing polishing pad

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