JPS6449459A - Timing synchronization circuit for modem - Google Patents

Timing synchronization circuit for modem

Info

Publication number
JPS6449459A
JPS6449459A JP62207276A JP20727687A JPS6449459A JP S6449459 A JPS6449459 A JP S6449459A JP 62207276 A JP62207276 A JP 62207276A JP 20727687 A JP20727687 A JP 20727687A JP S6449459 A JPS6449459 A JP S6449459A
Authority
JP
Japan
Prior art keywords
deviation
phase
correction
polarity
reception timing
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP62207276A
Other languages
Japanese (ja)
Inventor
Ario Okada
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Sanyo Electric Co Ltd
Original Assignee
Sanyo Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Sanyo Electric Co Ltd filed Critical Sanyo Electric Co Ltd
Priority to JP62207276A priority Critical patent/JPS6449459A/en
Publication of JPS6449459A publication Critical patent/JPS6449459A/en
Pending legal-status Critical Current

Links

Landscapes

  • Digital Transmission Methods That Use Modulated Carrier Waves (AREA)
  • Synchronisation In Digital Transmission Systems (AREA)

Abstract

PURPOSE:To take the timing synchronization of a modem, by providing a means to calculate a fine correction travel quantity and perform fine correction in a direction of deviation other than respective means for sampling, the polarity inspection of a sampled value, the discrimination of phase deviation at a sampling point, the calculation of the maximum deviation range, the specification of an error range, and the calculation and the correction of a phase shift quantity. CONSTITUTION:An A/D converter 10 samples the signal of transmission waveform of an amplifier 9 setting a reception timing phase as reference by a frequency of N times the modulation speed of a counter 21, and a control circuit 20 investigates the polarity of the sampled value at the sampling point obtained by a converter 19 from the output of a filter part 18 while the reception timing phase changes by 2pi, and discriminates the deviation of a reception timing in an inter-sample unit, and calculates respective maximum discrimination error range at the even and odd numbers of N by the maximum number of the sampling point with the same polarity decided by N and 2pi/N, and computes a coarse correction phase shift quantity by specifying a deviation discrimination error range. By detecting the micro deviation direction of the reception timing phase after initial correction, a phase difference can be calculated and corrected. The phase shift quantity on which coarse and fine correction is applied can be obtained only by the inspection of polarity and arithmetic operation without referring to a memory, and the synchronization of the reception and transmission timing phases can be obtained rapidly and with high accuracy.
JP62207276A 1987-08-20 1987-08-20 Timing synchronization circuit for modem Pending JPS6449459A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP62207276A JPS6449459A (en) 1987-08-20 1987-08-20 Timing synchronization circuit for modem

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP62207276A JPS6449459A (en) 1987-08-20 1987-08-20 Timing synchronization circuit for modem

Publications (1)

Publication Number Publication Date
JPS6449459A true JPS6449459A (en) 1989-02-23

Family

ID=16537112

Family Applications (1)

Application Number Title Priority Date Filing Date
JP62207276A Pending JPS6449459A (en) 1987-08-20 1987-08-20 Timing synchronization circuit for modem

Country Status (1)

Country Link
JP (1) JPS6449459A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2011030204A (en) * 2009-07-27 2011-02-10 Lsi Corp System and method for two tier sampling correction in data processing circuit

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2011030204A (en) * 2009-07-27 2011-02-10 Lsi Corp System and method for two tier sampling correction in data processing circuit

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