JPS6445351U - - Google Patents

Info

Publication number
JPS6445351U
JPS6445351U JP14076687U JP14076687U JPS6445351U JP S6445351 U JPS6445351 U JP S6445351U JP 14076687 U JP14076687 U JP 14076687U JP 14076687 U JP14076687 U JP 14076687U JP S6445351 U JPS6445351 U JP S6445351U
Authority
JP
Japan
Prior art keywords
subcode processing
subcode
diagram showing
system control
format
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP14076687U
Other languages
Japanese (ja)
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed filed Critical
Priority to JP14076687U priority Critical patent/JPS6445351U/ja
Publication of JPS6445351U publication Critical patent/JPS6445351U/ja
Pending legal-status Critical Current

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  • Signal Processing For Digital Recording And Reproducing (AREA)

Description

【図面の簡単な説明】[Brief explanation of the drawing]

第1図は、この考案の一実施例を示すブロツク
図である。第2図は、R―DATのトラツクフオ
ーマツトを示す図である。第3図は、第2図にお
けるPCM領域のフオーマツトを示す図である。
第4図は、第2図におけるサブコード領域のフオ
ーマツトを示す図である。第5図は、サブコード
領域のフオーマツトの詳細を示す図である。第6
図は、プログラムタイムについてのパツクフオー
マツトを示す図である。第7図は、従来回路を示
すブロツク図である。 14……主CPU(システムコントロール用C
PU)、30……PACK CPU。
FIG. 1 is a block diagram showing one embodiment of this invention. FIG. 2 is a diagram showing the track format of R-DAT. FIG. 3 is a diagram showing the format of the PCM area in FIG. 2.
FIG. 4 is a diagram showing the format of the subcode area in FIG. 2. FIG. 5 is a diagram showing details of the format of the subcode area. 6th
The figure shows a pack format for program time. FIG. 7 is a block diagram showing a conventional circuit. 14...Main CPU (system control C
PU), 30...PACK CPU.

Claims (1)

【実用新案登録請求の範囲】[Scope of utility model registration request] システムコントロール用CPUとは別個に設け
たサブコード処理用CPUによりサブコード処理
の一部または全部を行なうことを特徴とするサブ
コード処理回路。
A subcode processing circuit characterized in that part or all of subcode processing is performed by a subcode processing CPU provided separately from a system control CPU.
JP14076687U 1987-09-14 1987-09-14 Pending JPS6445351U (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP14076687U JPS6445351U (en) 1987-09-14 1987-09-14

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP14076687U JPS6445351U (en) 1987-09-14 1987-09-14

Publications (1)

Publication Number Publication Date
JPS6445351U true JPS6445351U (en) 1989-03-20

Family

ID=31405240

Family Applications (1)

Application Number Title Priority Date Filing Date
JP14076687U Pending JPS6445351U (en) 1987-09-14 1987-09-14

Country Status (1)

Country Link
JP (1) JPS6445351U (en)

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