JPS6442483U - - Google Patents

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Publication number
JPS6442483U
JPS6442483U JP13789087U JP13789087U JPS6442483U JP S6442483 U JPS6442483 U JP S6442483U JP 13789087 U JP13789087 U JP 13789087U JP 13789087 U JP13789087 U JP 13789087U JP S6442483 U JPS6442483 U JP S6442483U
Authority
JP
Japan
Prior art keywords
circulator
transmitting
circuit
receiver
signal
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP13789087U
Other languages
Japanese (ja)
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed filed Critical
Priority to JP13789087U priority Critical patent/JPS6442483U/ja
Publication of JPS6442483U publication Critical patent/JPS6442483U/ja
Pending legal-status Critical Current

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  • Radar Systems Or Details Thereof (AREA)

Description

【図面の簡単な説明】[Brief explanation of drawings]

第1図はこの考案の一実施例によるパルスレー
ダ装置を示す構成図、第2図は第1図中の受信系
試験モジユールの構成図、第3図は送受信モジユ
ールの構成図、第4図は従来のパルスレーダ装置
を示す構成図である。 1は励振機、2は送受切換器、3は受信機、4
はアレーアンテナ部、5は給電回路、6は送受信
モジユール、7は素子アンテナ、8はバス基板、
9はモジユール制御回路、10は受信系試験モジ
ユール、11a,11bは入出力端子、12は移
相器、13a,13bはサーキユレータ、14は
遅延回路、15は受信系保護用スイツチ、16は
受信系増幅器、17は駆動回路、18は終端、1
9は送信系増幅器、20は擬似信号発生器、21
はカツプラである。なお、図中、同一符号は同一
、又は相当部分を示す。
Fig. 1 is a block diagram showing a pulse radar device according to an embodiment of this invention, Fig. 2 is a block diagram of the receiving system test module in Fig. 1, Fig. 3 is a block diagram of the transmitting/receiving module, and Fig. 4 is a block diagram of the receiving system test module in Fig. 1. FIG. 1 is a configuration diagram showing a conventional pulse radar device. 1 is an exciter, 2 is a transmitter/receiver switch, 3 is a receiver, 4
is an array antenna section, 5 is a feeding circuit, 6 is a transmitting/receiving module, 7 is an element antenna, 8 is a bus board,
9 is a module control circuit, 10 is a receiving system test module, 11a, 11b are input/output terminals, 12 is a phase shifter, 13a, 13b are circulators, 14 is a delay circuit, 15 is a receiving system protection switch, 16 is a receiving system amplifier, 17 is a drive circuit, 18 is a termination, 1
9 is a transmission system amplifier, 20 is a pseudo signal generator, 21
is Katsupura. In addition, in the figures, the same reference numerals indicate the same or equivalent parts.

Claims (1)

【実用新案登録請求の範囲】[Scope of utility model registration request] 送信信号を発生する励振機と、上記励振機から
の送信信号を受け、多数の端子に送信信号を分配
する給電回路と、上記給電回路の多数の端子に接
続された多数の送受信モジユールと、上記送受信
モジユールに接続し、入力された送信信号を空間
に放射する、同一面内に多数配列された素子アン
テナと、空間から上記素子アンテナと送受信モジ
ユールを介して入力し、上記給電回路で合成され
た受信信号を受け、処理を行なう受信機と、上記
受信機及び励振機に接続し、上記給電回路との接
続を切り換える送受切換器と、上記送受信モジユ
ールを制御する信号を発生するモジユール制御回
路と、上記モジユール制御回路からの信号を上記
多数の送受信モジユールに配分するバス基板から
なるパルスレーダ装置において、上記送受信モジ
ユールが配列されたアレーアンテナ部の一部に、
送受信信号が通る移相器と、上記移送器に接続し
信号の方向を切り分ける第一のサーキユレータと
、上記第一のサーキユレータに接続し、送信信号
を遅らせる遅延回路と、上記遅延回路に接続し、
送受信信号を切り分ける第二のサーキユレータと
、上記第二のサーキユレータと接続する受信系保
護用スイツチと、上記第一のサーキユレータと上
記受信系保護用スイツチとに接続し、受信信号を
増幅する受信系増幅器と、制御信号により構成品
を制御する駆動回路とからなる受信系試験モジユ
ールを、上記第二のサーキユレータ側を上記素子
アンテナに、上記移相送器側を上記給電回路に接
続するように配置したことを特徴とするパルスレ
ーダ装置。
an exciter that generates a transmission signal; a power supply circuit that receives the transmission signal from the exciter and distributes the transmission signal to a large number of terminals; a large number of transmitting and receiving modules connected to the large number of terminals of the power supply circuit; A plurality of element antennas arranged in the same plane are connected to the transmitting/receiving module and radiate inputted transmitting signals into space; a receiver that receives and processes a received signal; a transmitter/receiver switch that is connected to the receiver and the exciter and switches the connection to the power supply circuit; and a module control circuit that generates a signal that controls the transmitter/receiver module; In a pulse radar device comprising a bus board that distributes signals from the module control circuit to the plurality of transmitting and receiving modules, a part of the array antenna section in which the transmitting and receiving modules are arranged,
a phase shifter through which the transmitted and received signals pass; a first circulator connected to the shifter to separate the direction of the signal; a delay circuit connected to the first circulator to delay the transmitted signal; and a delay circuit connected to the delay circuit;
a second circulator for separating transmitted and received signals; a receiving system protection switch connected to the second circulator; and a receiving system amplifier connected to the first circulator and the receiving system protection switch to amplify the received signal. and a drive circuit that controls the components using control signals, the receiver system test module is arranged such that the second circulator side is connected to the element antenna and the phase shift transmitter side is connected to the feeder circuit. A pulse radar device characterized by:
JP13789087U 1987-09-09 1987-09-09 Pending JPS6442483U (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP13789087U JPS6442483U (en) 1987-09-09 1987-09-09

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP13789087U JPS6442483U (en) 1987-09-09 1987-09-09

Publications (1)

Publication Number Publication Date
JPS6442483U true JPS6442483U (en) 1989-03-14

Family

ID=31399727

Family Applications (1)

Application Number Title Priority Date Filing Date
JP13789087U Pending JPS6442483U (en) 1987-09-09 1987-09-09

Country Status (1)

Country Link
JP (1) JPS6442483U (en)

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