JPS6441921U - - Google Patents
Info
- Publication number
- JPS6441921U JPS6441921U JP7385487U JP7385487U JPS6441921U JP S6441921 U JPS6441921 U JP S6441921U JP 7385487 U JP7385487 U JP 7385487U JP 7385487 U JP7385487 U JP 7385487U JP S6441921 U JPS6441921 U JP S6441921U
- Authority
- JP
- Japan
- Prior art keywords
- semiconductor switch
- frame
- disconnector
- disconnects
- operating lever
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 claims description 10
- 238000010586 diagram Methods 0.000 description 4
- 238000011017 operating method Methods 0.000 description 2
- 238000007689 inspection Methods 0.000 description 1
Landscapes
- Electronic Switches (AREA)
- Connections Arranged To Contact A Plurality Of Conductors (AREA)
- Switch Cases, Indication, And Locking (AREA)
Description
第１図は本考案の実施例の半導体スイツチユニ
ツトの正面図で、第２図は側面図である。第３図
は本考案の実施例のモジユールの側面図で、第４
図ａおよびｂは点検時の動作手順を示したもので
、第５図は三相回路に用いられた半導体スイツチ
の回路図で、第６図は本考案の実施例に用いた断
路器の外観図である。
１……断路器、１ａ……断路器操作レバー、３
……２次側端子カバー、３ａ……欠切部、３ｂ…
…蝶番、６……モジユール（フレームボツクス）
、８……モジユールカバー、１２……ピンヒンジ
。
FIG. 1 is a front view of a semiconductor switch unit according to an embodiment of the present invention, and FIG. 2 is a side view. Figure 3 is a side view of the module according to the embodiment of the present invention;
Figures a and b show the operating procedure during inspection, Figure 5 is a circuit diagram of a semiconductor switch used in a three-phase circuit, and Figure 6 is an external appearance of a disconnector used in an embodiment of the present invention. It is a diagram. 1... Disconnector, 1a... Disconnector operating lever, 3
...Secondary side terminal cover, 3a...Cutout, 3b...
...Hinge, 6...Module (frame box)
, 8...Module cover, 12...Pin hinge.
補正 昭６３．１０．１５
図面の簡単な説明を次のように補正する。
明細書第１５頁１０行目乃至第１６頁１行目迄
の全文を削除して、以下の字句を挿入する。「第
１図は本考案の実施例の半導体スイツチユニツト
の正面図、第２図は側面図、第３図は本考案の実
施例のモジユールの正面図、第４図はモジユール
の側面図、第５図ａおよびｂは半導体スイツチユ
ニツトの点検時の操作手順を示したもの、第６図
は三相回路に用いた半導体スイツチの配線図、第
７図は本実施例に用いた断路器の外観図である。
」Amendment October 15, 1981 The brief description of the drawing is amended as follows. The entire text from page 15, line 10 to page 16, line 1 of the specification is deleted and the following phrase is inserted. 1 is a front view of a semiconductor switch unit according to an embodiment of the present invention, FIG. 2 is a side view, FIG. 3 is a front view of a module according to an embodiment of the present invention, and FIG. 4 is a side view of the module. Figures 5a and b show the operating procedure when inspecting the semiconductor switch unit, Figure 6 is the wiring diagram of the semiconductor switch used in the three-phase circuit, and Figure 7 is the external appearance of the disconnector used in this example. It is a diagram.
”
Claims (1)
体スイツチの断接を制御する制御部とをフレーム
に収容して単体のフレームボツクスを形成し、前
記半導体スイツチが電気回路を断とした時の２次
側に印加されている回路電圧を断接する断路器を
備えた枠体に前記フレームボツクスを収容して半
導体スイツチユニツトを構成し、前記枠体の下端
部に前記断路器を操作レバーが枠体前面に突出す
るように固設すると共に、該断路器の操作レバー
が回路電圧を接とする位置にある時該操作レバー
に当接する形状の欠切部を形成した端子カバーを
枠体前面に蝶着したことを特徴とする半導体スイ
ツチユニツト。 A semiconductor switch that connects or disconnects an electric circuit and a control unit that controls the connection or disconnection of the semiconductor switch are housed in a frame to form a single frame box, and when the semiconductor switch disconnects the electric circuit, the secondary side A semiconductor switch unit is constituted by housing the frame box in a frame body equipped with a disconnector that connects and disconnects the circuit voltage applied to the circuit, and the disconnector is attached to the lower end of the frame body, and the operating lever is attached to the front surface of the frame body. A terminal cover is fixedly installed so as to protrude and is hinged to the front surface of the frame, and has a notch shaped to abut the operating lever of the disconnector when the operating lever is in a position where it contacts the circuit voltage. A semiconductor switch unit characterized by:
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP7385487U JPS6441921U (en) | 1987-05-18 | 1987-05-18 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP7385487U JPS6441921U (en) | 1987-05-18 | 1987-05-18 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS6441921U true JPS6441921U (en) | 1989-03-13 |
Family
ID=31298984
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP7385487U Pending JPS6441921U (en) | 1987-05-18 | 1987-05-18 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS6441921U (en) |
-
1987
- 1987-05-18 JP JP7385487U patent/JPS6441921U/ja active Pending
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