JPS644122B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a mask line cutting information generating circuit that can be suitably used in an automatic visual inspection device for articles, a sorting device, and other image processing devices.

2. Description of the Related Art Conventionally, image processing apparatuses that process optical, electrical, magnetic, and other two-dimensional image information constituted by a two-dimensional array have been used for automatic visual inspection of articles and the like. This type of processing device generally includes an image input means for capturing a two-dimensional pattern by repeating horizontal scanning an appropriate number of times in the vertical direction, means for quantizing the video signal from the image input means to generate a quantized video signal, and a means for generating a quantized video signal by quantizing the video signal from the image input means. Processing means are provided for processing the quantized video signal. Furthermore, many of these image processing apparatuses are equipped with mask area generation means to improve processing accuracy. That is, this mask area generating means blocks the video signal or quantized video signal corresponding to a position outside the set mask area, removes noise caused by non-inspection objects, and improves processing accuracy. Conventional equipment does not have a circuit to detect the suitability of the mask, and if the position of the item varies and a non-inspected object enters the mask area, or if the object to be inspected protrudes from the mask area, it may actually be a non-defective item. Despite this, there is a risk that the product will be judged as defective, resulting in a reduction in inspection accuracy.

This invention was made in view of the above-mentioned conventional drawbacks, and its purpose is to detect the suitability of a set mask and to provide judgment data for automatically resetting the mask if necessary. An object of the present invention is to provide a mask line cutting information generating circuit that can quantitatively display the degree of inappropriateness of a mask. The details of the present invention will be explained below with reference to the drawings.

FIG. 1 is a conceptual diagram for explaining the principle of the present invention. The area surrounded by the outermost rectangle is the effective screen, and the inside thereof includes the inspection object 1 as well as the non-inspection objects 2 and 3. Therefore, it is necessary to set an appropriate mask area to shield these non-inspection objects. However, as shown in the figure, the actually set mask area ABCD is too large and includes part of the non-inspection objects 2 and 3. On the contrary, if the mask area ABCD is too small, the inspection object 1 will protrude from the mask area, which is inappropriate.

The present invention focuses on the point that if the setting of the mask area is inappropriate, but not extremely inappropriate, the mask line will inevitably be cut or touched by the object to be inspected or the object not to be inspected. If the setting of the mask area is significantly shifted to include all non-inspection objects, such cutting of the mask line will not occur. However, since the variation in the position or size of the object is usually relatively small, the cutting information of the mask line is effective information in determining the suitability of the mask.

FIGS. 2 and 3 are a block diagram of an embodiment of the present invention and waveform diagrams for explaining the operation of this circuit. Mask line coordinate latch circuits 10, 11,
12 and 13 are each bus 20 from CPU 19
Mask line coordinates X ₁ , X ₂ , given in advance via
Y ₁ and Y ₂ (see Figure 1) are latched, and each latched mask line coordinate is sent to the mask line signal generation circuit 1.
Supply to 4. The mask line signal generation circuit 14 receives the supplied mask line coordinates and the basic clock circuit 1.
a horizontal coordinate counter 40 that counts the basic clock signal supplied from the horizontal coordinate counter 40, and a vertical coordinate counter 4 that counts the signal output from the horizontal coordinate counter 40 every time the count for one horizontal scan is completed.
1, and comparators 42 and 43 that compare the count value of the horizontal coordinate counter 40 and the mask line coordinates X ₁ and X ₂ latched in the latch circuits 10 and 11.
, the count value of the vertical coordinate counter 41 and the mask line coordinates latched in the latch circuits 12 and 13.
It is composed of comparators 44 and 45 that compare Y ₁ and Y ₂ . Each comparator 42 to 45
When the count value of the counter 40 or 41 matches the coordinate value input to the latch circuit, the third
Mask line signals AB, BC, CD and
Generate DA. The mask line signals BC and DA are normally used mask signals themselves, whereas the mask line signals AB and CD have a width approximately equal to the clock width that indicates the rise and fall points of the normal mask signal, respectively. It's a pulse. Each of these mask line signals is passed through the AND gates 20, 2
1, 22 and 23, respectively.

Further, a signal outputted from the horizontal coordinate counter 40 every time the count for one horizontal scan is completed, and a signal outputted from the vertical coordinate counter 41 every time the count for one screen is completed are transmitted to the camera external synchronization signal generation circuit 18. and based on these signals, the camera external synchronization signal generation circuit 18 outputs the image input means 16.
outputs synchronization signals for horizontal and vertical scanning.

On the other hand, the video signal taken into the image input device 16 is quantized by the quantization circuit 17, and then
It is input to the second input terminal of each of AND gates 20, 21, 22 and 23. and gate 2
The outputs of 0, 21, 22 and 23 are supplied to counter circuits 30, 31, 32 and 33, respectively. Each of these counter circuits receives a basic clock signal supplied from the basic clock circuit 15, and counts the number of clocks received during the period when the output of the corresponding AND gate is logic "1". Each counter circuit 30 to 33 counts the total number of counts over one vertical scanning period.
Output NX1, NX2, NY1, and NY2 to the outside of the mask line cutting information generation circuit. The above count values NX1 to NY2 are information on the cutting length of the mask line depending on the target.

These mask line cutting length information NX1 to NY2 are
The data is supplied to other parts of the image processing apparatus and used as a criterion for determining whether or not the mask being set is appropriate and when resetting the mask. For example, the mask line cutting length information NX1 and the like are supplied to a comparison circuit within the image processing device and compared with a preset tolerance value. When cutting length information NX1 etc. exceeds the allowable value,
The image processing device can also interrupt the processing and notify the outside of the mask setting defect by an appropriate method.
Alternatively, when the cutting length signal exceeds a permissible value, the image processing device can reset an appropriate mask by changing the mask line coordinates by trial and error while monitoring changes in the cutting length. Furthermore, if it is desired to know only whether or not the mask has been cut, a 1-bit latch circuit can be provided in place of the counter circuits 30 to 33 in FIG. 2 to simplify the circuit.

As explained in detail above, the present invention can generate mask cutting information with a simple configuration of performing an AND operation between a mask line signal and a quantized video signal, so that the apparatus of the present invention can be used for image processing. It can be used in devices to contribute to improving image processing accuracy.

[Brief explanation of drawings]

FIG. 1 is a conceptual diagram for explaining the principle of the present invention, FIG. 2 is a block diagram of an embodiment of the present invention, and FIG. 3 is a waveform diagram for explaining the operation of FIG. 10 to 13...Mask line coordinate latch circuit, 1
4... Mask line signal generation circuit, 15... Basic clock signal generation circuit, 16... Image input means, 17
... Quantization circuit, 20 to 23 ... AND gate, 30 to 33 ... Counter circuit.

Claims (1)

[Claims] 1 Repeat the horizontal scan an appropriate number of times in the vertical direction and 2
an image input means for capturing a dimensional pattern; means for quantizing a video signal from the image input means to generate a quantized video signal; a horizontal direction and a mask signal for masking the video signal or the minimized video signal; means for generating horizontal and vertical mask line pulses indicative of vertical edges; logic means for ANDing the quantized video signal and the horizontal mask line pulses over a vertical scan period; , a mask line cutting information generating circuit comprising logic means for performing a logical product of the quantized video signal and the vertical mask line pulse.