JPS6440244U - - Google Patents
Info
- Publication number
- JPS6440244U JPS6440244U JP13407087U JP13407087U JPS6440244U JP S6440244 U JPS6440244 U JP S6440244U JP 13407087 U JP13407087 U JP 13407087U JP 13407087 U JP13407087 U JP 13407087U JP S6440244 U JPS6440244 U JP S6440244U
- Authority
- JP
- Japan
- Prior art keywords
- circuit
- switcher
- unit
- control unit
- data
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000001514 detection method Methods 0.000 claims description 2
- 238000010586 diagram Methods 0.000 description 3
Landscapes
- Studio Circuits (AREA)
- Stand-By Power Supply Arrangements (AREA)
Description
第1図は本考案のスイツチヤ制御回路の一実施
例を示すブロツク図、第2図は従来のスイツチヤ
制御回路の一例を示すブロツク図、第3図は第2
図におけるデータ保持時間の分布例を示す図であ
る。
1,8……スイツチヤユニツト、2,9……バ
ツクアツプ電源、3,10……リセツト検知回路
、4,11……データ保持回路、5……バツフア
回路、6……共通バス、7,13……制御ユニツ
ト。
FIG. 1 is a block diagram showing an embodiment of the switcher control circuit of the present invention, FIG. 2 is a block diagram showing an example of a conventional switcher control circuit, and FIG. 3 is a block diagram showing an example of the conventional switcher control circuit.
It is a figure which shows the distribution example of the data holding time in a figure. 1, 8... Switcher unit, 2, 9... Backup power supply, 3, 10... Reset detection circuit, 4, 11... Data holding circuit, 5... Buffer circuit, 6... Common bus, 7, 13 ...control unit.
Claims (1)
チヤユニツトと、これらスイツチヤユニツトを制
御する制御ユニツトにおいて、前記スイツチヤユ
ニツトはデータ保持回路と、バツクアツプ電圧を
検知して前記データを保持回路にリセツトをかけ
るリセツト検知回路と、このリセツト出力をバツ
フアを介して出力し前記制御ユニツトの再制御入
力に供給するバスラインとを備えることを特徴と
するスイツチヤ制御回路。 In a switcher unit with a plurality of battery backup functions and a control unit that controls these switcher units, the switcher unit has a data holding circuit and a reset circuit that detects the backup voltage and resets the data to the holding circuit. A switch control circuit comprising: a detection circuit; and a bus line for outputting the reset output via a buffer and supplying it to the re-control input of the control unit.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP13407087U JPS6440244U (en) | 1987-09-01 | 1987-09-01 |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP13407087U JPS6440244U (en) | 1987-09-01 | 1987-09-01 |
Publications (1)
Publication Number | Publication Date |
---|---|
JPS6440244U true JPS6440244U (en) | 1989-03-10 |
Family
ID=31392488
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP13407087U Pending JPS6440244U (en) | 1987-09-01 | 1987-09-01 |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS6440244U (en) |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH04137407U (en) * | 1991-06-12 | 1992-12-22 | 日本電設工業株式会社 | Simple closed type switchboard |
-
1987
- 1987-09-01 JP JP13407087U patent/JPS6440244U/ja active Pending
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH04137407U (en) * | 1991-06-12 | 1992-12-22 | 日本電設工業株式会社 | Simple closed type switchboard |
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