JPS6439154A - Digital radio trasmitter - Google Patents

Digital radio trasmitter

Info

Publication number
JPS6439154A
JPS6439154A JP62195609A JP19560987A JPS6439154A JP S6439154 A JPS6439154 A JP S6439154A JP 62195609 A JP62195609 A JP 62195609A JP 19560987 A JP19560987 A JP 19560987A JP S6439154 A JPS6439154 A JP S6439154A
Authority
JP
Japan
Prior art keywords
circuit
output signal
signal
pattern
ais
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP62195609A
Other languages
Japanese (ja)
Inventor
Hidemasa Yamauchi
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp filed Critical NEC Corp
Priority to JP62195609A priority Critical patent/JPS6439154A/en
Publication of JPS6439154A publication Critical patent/JPS6439154A/en
Pending legal-status Critical Current

Links

Landscapes

  • Detection And Prevention Of Errors In Transmission (AREA)
  • Maintenance And Management Of Digital Transmission (AREA)

Abstract

PURPOSE:To keep random properties of the output signal of a radio transmitter without affecting the necessary additional bits in the radio section, by applying the scrambling to the output signal of an elastic memory part via an PN pattern with an alarm state indication signal AIS. CONSTITUTION:An AIS detecting circuit 1 checks whether a digital data input signal 101 of a digital radio transmitter is equal to an AIS or not. The signal 101 is temporarily stored in an elastic memory part 2 for radio transfer. At the same time, a pseudo random pattern 105 produced by a PN pattern generating circuit 3 is multiplied 8 by a 1st timing signal of the circuit 1. The result of this multiplication is applied to a 2nd scramble circuit 4 and an output signal 102 of the part 2 is scrambled. An output signal 110 of the circuit 4 is multiplexed 6 by a 2nd timing signal of a timing generating circuit 15 and an output signal 108 is scrambled by a 1st scramble circuit 7 with a scramble pattern 107 produced by the circuit 15. Then an output signal 109 is outputted.
JP62195609A 1987-08-04 1987-08-04 Digital radio trasmitter Pending JPS6439154A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP62195609A JPS6439154A (en) 1987-08-04 1987-08-04 Digital radio trasmitter

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP62195609A JPS6439154A (en) 1987-08-04 1987-08-04 Digital radio trasmitter

Publications (1)

Publication Number Publication Date
JPS6439154A true JPS6439154A (en) 1989-02-09

Family

ID=16344007

Family Applications (1)

Application Number Title Priority Date Filing Date
JP62195609A Pending JPS6439154A (en) 1987-08-04 1987-08-04 Digital radio trasmitter

Country Status (1)

Country Link
JP (1) JPS6439154A (en)

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