JPS6435751U - - Google Patents

Info

Publication number

JPS6435751U

JPS6435751U JP12919087U JP12919087U JPS6435751U JP S6435751 U JPS6435751 U JP S6435751U JP 12919087 U JP12919087 U JP 12919087U JP 12919087 U JP12919087 U JP 12919087U JP S6435751 U JPS6435751 U JP S6435751U

Authority

JP

Japan

Prior art keywords

semiconductor chip

substrate

board

electrically connected

wiring pattern

Prior art date

1987-08-27

Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)

Pending

Links

• Espacenet
• Global Dossier
• Discuss

• 239000000758 substrate Substances 0.000 claims description 8
• 239000004065 semiconductor Substances 0.000 claims description 7
• 239000011347 resin Substances 0.000 claims 1
• 229920005989 resin Polymers 0.000 claims 1
• 238000010586 diagram Methods 0.000 description 2
• 238000007789 sealing Methods 0.000 description 2
• 238000007796 conventional method Methods 0.000 description 1
• 238000004519 manufacturing process Methods 0.000 description 1
• 238000000034 method Methods 0.000 description 1