JPS643237Y2 - - Google Patents

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Publication number
JPS643237Y2
JPS643237Y2 JP1981037996U JP3799681U JPS643237Y2 JP S643237 Y2 JPS643237 Y2 JP S643237Y2 JP 1981037996 U JP1981037996 U JP 1981037996U JP 3799681 U JP3799681 U JP 3799681U JP S643237 Y2 JPS643237 Y2 JP S643237Y2
Authority
JP
Japan
Prior art keywords
channel
contact
circuit
tuning
coil
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired
Application number
JP1981037996U
Other languages
Japanese (ja)
Other versions
JPS57151030U (en
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed filed Critical
Priority to JP1981037996U priority Critical patent/JPS643237Y2/ja
Publication of JPS57151030U publication Critical patent/JPS57151030U/ja
Application granted granted Critical
Publication of JPS643237Y2 publication Critical patent/JPS643237Y2/ja
Expired legal-status Critical Current

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  • Channel Selection Circuits, Automatic Tuning Circuits (AREA)
  • Input Circuits Of Receivers And Coupling Of Receivers And Audio Equipment (AREA)

Description

【考案の詳細な説明】 本考案はテレビジヨン受像機において使用する
VHFチユーナ、特にデイスクターレツト方式の
VHFチユーナの入力同調回路に関する。
[Detailed description of the invention] The invention is used in a television receiver.
VHF tuners, especially discret type
Regarding input tuning circuit of VHF tuner.

一般にVHFチユーナは第1図に示すように入
力端子1と入力同調回路2との間にIFトラツプ
3、FMトラツプ4、イメージトラツプ5等の
種々のトラツプ回路を設けている。このような
VHFチユーナの入力同調回路2を第2図に示す。
第2図において、6は前記トラツプ5に接続され
た第1固定接触バネであり、7は結合コンデンサ
Cbを介して高周波増幅回路に接続される第2固
定接触バネである。これらの固定接触バネ6,7
に対しチヤンネルごとに対になつた第1接点S12
〜S5,第2接点S′12〜S′5が順次当接することによ
りチヤンネル切換えが行なわれる。L12は第12チ
ヤンネルの同調コイルであり、第11チヤンネルの
同調コイルL11及び第10チヤンネルの同調コイル
L10は前記第12チヤンネルの同調コイルL12に対し
直列に接続されている。第9チヤンネルの同調コ
イルL9に対し第8チヤンネルの同調コイルL8
び第7チヤンネルの同調コイルL7も同様である。
また第6チヤンネルの同調コイルL6に対して第
5チヤンネルの同調コイルL5も同様に直列に接
続されている。各チヤンネルに共通のコイルLa
とコンデンサCaの直列回路はハイチヤンネル
(西ドイツでは第5チヤンネル〜第12チヤンネル)
受信時にローチヤンネル(西ドイツでは第2チヤ
ンネル〜第4チヤンネル)若しくはFMのトラツ
プを構成すると共にハイチヤンネル信号のマツチ
ング用としても動作する。この直列回路をLa′と
して受信チヤンネルの同調コイルをL0で代表さ
せて第5チヤンネル〜第12チヤンネルの等価回路
をかくと第3図のようになる。今、このチユーナ
がハイチヤンネルのHなる周波数に同調したとす
れば第4図に示すように各妨害信号IFFMに対
する選択特性は殆んど入力同調回路2の前に設け
たトラツプ回路3,4,5等によつて得られてい
る。従つて、ハイチヤンネルバンドに近接した妨
害信号で、例えばH±IF(ただしIFは中間周波
数)なる周波数の妨害に対しては第5図に示すよ
うな選択度特性しか得られないことになり、前記
の妨害信号を完全に阻止しえない。
Generally, a VHF tuner is provided with various trap circuits such as an IF trap 3, an FM trap 4, and an image trap 5 between an input terminal 1 and an input tuning circuit 2, as shown in FIG. like this
FIG. 2 shows the input tuning circuit 2 of the VHF tuner.
In FIG. 2, 6 is a first fixed contact spring connected to the trap 5, and 7 is a coupling capacitor.
A second fixed contact spring connected to the high frequency amplification circuit via Cb. These fixed contact springs 6,7
The first contacts S 12 are paired for each channel.
-S 5 and the second contacts S' 12 -S' 5 sequentially abut, thereby performing channel switching. L 12 is the tuning coil of the 12th channel, the tuning coil L 11 of the 11th channel and the tuning coil of the 10th channel.
L10 is connected in series to the tuning coil L12 of the twelfth channel. The same applies to the tuning coil L 9 of the ninth channel, the tuning coil L 8 of the eighth channel, and the tuning coil L 7 of the seventh channel.
Further, the tuning coil L 5 of the fifth channel is also connected in series with the tuning coil L 6 of the sixth channel. Coil La common to each channel
The series circuit of capacitor Ca and capacitor Ca is Haiti channel (5th channel to 12th channel in West Germany)
At the time of reception, it constitutes a low channel (2nd to 4th channel in West Germany) or FM trap, and also operates for matching high channel signals. If this series circuit is represented by La' and the tuning coil of the receiving channel is represented by L0 , the equivalent circuits of the 5th channel to the 12th channel are drawn as shown in FIG. Now, if this tuner is tuned to the H frequency of the high channel, the selection characteristics for each interference signal IF and FM will be mostly determined by the trap circuit 3, which is provided before the input tuning circuit 2, as shown in FIG. 4, 5, etc. Therefore, for interference signals close to the high channel band, for example at a frequency of H ± IF (where IF is the intermediate frequency), only the selectivity characteristics shown in Figure 5 can be obtained. The above-mentioned interfering signals cannot be completely blocked.

本考案は、このような欠点を除去するように工
夫したVHFチユーナを提案するものである。
The present invention proposes a VHF tuner devised to eliminate these drawbacks.

以下図面に示した実施例に従つて説明する。第
6図に示すように本考案ではハイバンドチヤンネ
ルの中ほどのチヤンネル(図示では第10チヤンネ
ル)の第1接点S10と、それより1つ低い第9チ
ヤンネルの第1接点S9との間にコンデンサCx0
コイルLx0とよりなる近接周波数の妨害信号を阻
止する並列トラツプ回路8を接続している。尚第
10チヤンネルの第1接点S10と第9チヤンネルの
第2接点S′9との間に第9チヤンネルの同調コイ
ルL9を接続している。斯る構成によれば第9チ
ヤンネル〜第7チヤンネルでは第7図に示すよう
な等価回路となり、並列トラツプ回路8によつて
近接妨害信号は好適に除去される。このときの選
択特性を第8図に示す。第8図において、Dは受
信チヤンネルの周波数、実線9はトラツプ回路8
の共振点Uiが同調周波数Dに比べて高い場合を、
破線10はDに比べて低い場合をそれぞれ示して
いる。第6図の如く第7チヤンネル〜第9チヤン
ネルにおいて近接妨害を取り除くようにするが、
第6チヤンネル及び第5チヤンネルでは不要であ
る場合には第6チヤンネルの第1接点S6と第11チ
ヤンネルの第1接点S11との間は導線11で短絡
する。
The following will explain the embodiments shown in the drawings. As shown in FIG. 6, in the present invention, between the first contact point S10 of the middle channel of the high band channel (the 10th channel in the illustration) and the first contact point S9 of the 9th channel one level lower than that. A parallel trap circuit 8 consisting of a capacitor C x0 and a coil L x0 is connected to block interference signals of adjacent frequencies. Shang No.
A tuning coil L9 of the ninth channel is connected between the first contact S10 of the tenth channel and the second contact S'9 of the ninth channel. With this configuration, the ninth to seventh channels have an equivalent circuit as shown in FIG. 7, and the parallel trap circuit 8 effectively removes the proximity interference signal. The selection characteristics at this time are shown in FIG. In Figure 8, D is the frequency of the receiving channel, and solid line 9 is the trap circuit 8.
When the resonance point Ui of is higher than the tuning frequency D ,
Broken lines 10 indicate cases lower than D. Proximity interference is removed from the 7th channel to the 9th channel as shown in Figure 6.
When the sixth channel and the fifth channel are not required, the first contact S 6 of the sixth channel and the first contact S 11 of the eleventh channel are short-circuited with a conductive wire 11 .

第9図の実施例では第1接点及び第2接点を設
けたデイスクターレツト板(図示せず)に更に補
助端子12を設け、この補助端子12と第6チヤ
ンネルの第2接点S′6との間に第6チヤンネルの
同調コイルL6を接続すると共に補助端子12と
第6チヤンネルの第1接点S6との間にコンデンサ
C×1とコイルL×1とよりなる第2の並列トラツプ
13を設けている。また短絡線11は前記補助端
子12に接続している。従つて第9チヤンネル〜
第7チヤンネル受信時には並列トラツプ回路8
が、また第6チヤンネル〜第5チヤンネル受信時
には第2並列トラツプ回路13が、それぞれのチ
ヤンネルの前に挿入されて近接妨害信号を阻止す
るように働く。
In the embodiment shown in FIG. 9, an auxiliary terminal 12 is further provided on the discrete plate (not shown) provided with the first and second contacts, and this auxiliary terminal 12 is connected to the second contact S' 6 of the sixth channel. A tuning coil L 6 of the sixth channel is connected between the two, and a capacitor is connected between the auxiliary terminal 12 and the first contact S 6 of the sixth channel.
A second parallel trap 13 consisting of C ×1 and coil L ×1 is provided. Further, the shorting line 11 is connected to the auxiliary terminal 12. Therefore, the 9th channel~
Parallel trap circuit 8 when receiving the 7th channel
However, when receiving the sixth to fifth channels, the second parallel trap circuit 13 is inserted before each channel and works to block proximity interference signals.

第10図の実施例では第2トラツプ回路13を
第7チヤンネルの第1接点S7と第6チヤンネルの
第1接点S6との間に挿入している。また第7チヤ
ンネル及び第6チヤンネルの第2接点S′7,S′6
に第6チヤンネルの同調コイルL6をつなぐと共
に第8チヤンネルの第1接点S8とアース間にコン
デンサCyを接続している。従つて第9チヤンネ
ル〜第7チヤンネル受信時には第11図のような
等価回路となり、その選択特性は第12図とな
る。また第6チヤンネル〜第5チヤンネル受信時
の等価回路は第13図、その特択特性は第14図
の如く第2並列トラツプ回路13による減衰(共
振点U2)が第1並列トラツプ回路8のU1と併存
した形となる。
In the embodiment of FIG. 10, the second trap circuit 13 is inserted between the first contact S7 of the seventh channel and the first contact S6 of the sixth channel. In addition, the tuning coil L 6 of the 6th channel is connected between the second contacts S' 7 and S' 6 of the 7th channel and the 6th channel, and the capacitor Cy is connected between the first contact S 8 of the 8th channel and the ground. ing. Therefore, when receiving channels from the 9th channel to the 7th channel, the equivalent circuit becomes as shown in FIG. 11, and its selection characteristics become as shown in FIG. 12. Further, the equivalent circuit when receiving channels 6 to 5 is shown in FIG. 13, and its special characteristic is shown in FIG. It coexists with

以上の通り本考案によればデイスクターレツト
型VHFチユーナにおける同調コイルの切換え構
造中に並列トラツプ回路を設けたので受信チヤン
ネルに近接した妨害信号を好適に除去することが
でき極めて有効である。
As described above, according to the present invention, since a parallel trap circuit is provided in the switching structure of the tuning coil in a discrete VHF tuner, it is possible to suitably remove interference signals close to the receiving channel, which is extremely effective.

【図面の簡単な説明】[Brief explanation of the drawing]

第1図はVHFチユーナの入力側回路を一般的
に説明するためのブロツク図であり、第2図は従
来のVHFチユーナの要部の回路図、第3図はそ
の等価回路図、第4図及び第5図はその説明図で
ある。第6図は本考案を実施したVHFチユーナ
の要部回路図、第7図はその等価回路図、第8図
はその選択特性図である。第9図は本考案の他の
実施例の要部回路図である。第10図は更に本考
案の他の実施例の要部回路図であり、第11図、
第12図、第13図及び第14図はその説明図で
ある。 1……入力端子、2……入力同調回路、6,7
……第1第2固定接触バネ、8,13……並列ト
ラツプ回路、L12〜L5……同調コイル、S12〜S5
…第1接点、S′12〜S′5……第2接点。
Figure 1 is a block diagram for generally explaining the input side circuit of a VHF tuner, Figure 2 is a circuit diagram of the main parts of a conventional VHF tuner, Figure 3 is its equivalent circuit diagram, and Figure 4. and FIG. 5 are explanatory diagrams thereof. FIG. 6 is a circuit diagram of a main part of a VHF tuner embodying the present invention, FIG. 7 is an equivalent circuit diagram thereof, and FIG. 8 is a selection characteristic diagram thereof. FIG. 9 is a circuit diagram of a main part of another embodiment of the present invention. FIG. 10 is a circuit diagram of a main part of another embodiment of the present invention, and FIG.
FIG. 12, FIG. 13, and FIG. 14 are explanatory diagrams thereof. 1...Input terminal, 2...Input tuning circuit, 6, 7
...First and second fixed contact springs, 8, 13...Parallel trap circuit, L12 to L5 ...Tuning coil, S12 to S5 ...
...first contact, S' 12 to S' 5 ... second contact.

Claims (1)

【実用新案登録請求の範囲】[Scope of utility model registration request] 各チヤンネルに応じて同調コイルの値を切換え
るため第1第2固定接触バネによつて入力端子側
と出力端子側にそれぞれ接続される第1第2接点
を各チヤンネル毎に一対づつ有する入力同調回路
を備えるデイスクターレツト方式のVHFチユー
ナに於いて、VHFハイバンド内の中ほどのチヤ
ンネルに対応する上記入力同調回路の第1接点と
該チヤンネルよりも1チヤンネル高いチヤンネル
に対応する第1接点との間にコイルとコンデンサ
よりなる近接周波数妨害除去用の並列トラツプ回
路を接続すると共に、前記中ほどのチヤンネルの
第1接点と前記1チヤンネル高いチヤンネルの第
2接点との間にその1チヤンネル高いチヤンネル
用の同調コイルを接続したことを特徴とする
VHFチユーナ。
An input tuning circuit having a pair of first and second contacts for each channel, each connected to the input terminal side and the output terminal side by a first and second fixed contact spring in order to switch the value of the tuning coil according to each channel. In a discret type VHF tuner, the first contact of the input tuning circuit corresponds to a channel in the middle of the VHF high band, and the first contact corresponds to a channel one channel higher than the channel. A parallel trap circuit for removing near-frequency interference consisting of a coil and a capacitor is connected between them, and between the first contact of the middle channel and the second contact of the channel one channel higher than the one channel higher. It is characterized by connecting a tuning coil of
VHF Chuyuna.
JP1981037996U 1981-03-17 1981-03-17 Expired JPS643237Y2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP1981037996U JPS643237Y2 (en) 1981-03-17 1981-03-17

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP1981037996U JPS643237Y2 (en) 1981-03-17 1981-03-17

Publications (2)

Publication Number Publication Date
JPS57151030U JPS57151030U (en) 1982-09-22
JPS643237Y2 true JPS643237Y2 (en) 1989-01-27

Family

ID=29835169

Family Applications (1)

Application Number Title Priority Date Filing Date
JP1981037996U Expired JPS643237Y2 (en) 1981-03-17 1981-03-17

Country Status (1)

Country Link
JP (1) JPS643237Y2 (en)

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS547447U (en) * 1977-06-20 1979-01-18

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS547447U (en) * 1977-06-20 1979-01-18

Also Published As

Publication number Publication date
JPS57151030U (en) 1982-09-22

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