JPS643091B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION [Technical Field of the Invention] The present invention relates to a current input type impedance conversion circuit having an input impedance proportional to a load impedance, and particularly to an impedance conversion circuit most suitable for integration into an integrated circuit. [Technical background of the invention and its problems] As shown in FIG. 1 as a four-terminal network, an impedance conversion circuit has an output voltage V ₂ and an output current I ₂ for an input voltage V ₁ and an input current I ₁ . has a proportional relationship with the load impedance, and its operation is shown by the transfer matrix below. In the above equation (1), A≠0, D≠0, B=C=
A circuit in which the impedance becomes 0 is called an impedance conversion circuit. In FIG. 1, V _IN is the input voltage source and Z _S is the input impedance. By the way, a device that satisfies the above relationship and can actually be integrated into a circuit using bipolar elements has not yet been realized, and such a device is currently in great demand. [Purpose of the Invention] The present invention was made in consideration of the above-mentioned circumstances, and its purpose is to provide an impedance conversion circuit that is most suitable for integration into an integrated circuit. The object of the present invention is to provide an impedance conversion circuit suitable for. [Summary of the Invention] According to an embodiment of the present invention, the emitter of an input PNP transistor is connected to the input terminal, the base is connected to the output terminal, and a current approximately equal to the current inputted from the collector to the input terminal is generated. output,
This current is input to the first current mirror circuit to output a current proportional to this current from its output side, and this output current is input to the second current mirror circuit to output this current from its output side. By outputting a current proportional to , outputting this output current from the output terminal, and applying the voltage of the input terminal to this output terminal via the emitter-base coupling of the input PNP transistor, An impedance conversion circuit is provided that has an input impedance proportional to the impedance of a load circuit connected to an output terminal. [Embodiment of the Invention] An embodiment of the invention will be described below with reference to the drawings. FIG. 2 is a circuit diagram showing its configuration. In the figure, 1 is an input terminal and 2 is an output terminal. Input terminal 1 is connected to an input current source 3 that provides an input current _I1 , and there is a voltage Z _L between the output terminal 2 and the low potential V _S application point. A load circuit 4 having impedance is inserted. The input terminal 1 above has an additional input terminal.
The emitter of the pnp transistor 5 is connected, and the base of this transistor 5 is connected to the output terminal 2. Furthermore, the collector of the transistor 5 is connected to a pair of npn transistors constituting a current mirror circuit 6 .
Of the transistors 7 and 8, it is connected to the collector of the transistor 7 on the input side. This current mirror circuit 6 connects the bases of the transistors 7 and 8 in common, shorts the collector and base of the transistor 7, connects the emitter of the transistor 7 to the V _S application point, and connects the output side transistor. 8 emitter through emitter resistor 9 to V _S
It is configured by connecting to the application point. The collector of the transistor 8 is connected to a pair of pnp transistors 11 and 1 constituting another current mirror circuit 10.
2, it is connected to the collector of the transistor 11 on the input side. This current mirror circuit 10 is
The bases of both transistors 11 and 12 are commonly connected, the collector and base of transistor 11 are short-circuited, and the emitters of both transistors 11 and 12 are connected to a high potential V _C application point. The collector of the output transistor 12 of the current mirror circuit 10 is connected to the output terminal 2. In addition, two current mirror circuits 6 and 10
Each pair of transistors 7 and 8 and 1 constitute
1 and 12 are designed to have the same emitter area. In such a configuration, if the common base current amplification factor α of the input PNP transistor 5 is approximately 1, the collector current of this transistor 5 will be equal to its emitter current, that is, the input current I ₁ from the input current source 3. . Therefore, a current equal to the input current _I1 is input to the input side of the current mirror circuit 6 , and the input current is input to the output side of the current mirror circuit 6.
A current I ₃ proportional to I ₁ will flow into it. This current I ₃ becomes the input current of another current mirror circuit 10 , and from its output side, the input current I ₃
A current I ₂ proportional to flows out. and this current I ₂
is input to the load circuit 4 via the output terminal 2. Here, the current transmission ratios of the current mirror circuits 6 and 10 are respectively γ ₁ and γ ₂ , and the current flowing into the input terminal 1 is a positive polarity current, and the current flowing out from the output terminal 2 is a negative polarity current. Then,
The output current I ₂ is given by the following equation. −I ₂ = γ ₁・γ ₂・I ₁ …(2) On the other hand, the voltage V ₂ at the output terminal 2 is determined by the impedance Z _L of the load circuit 4 and the current flowing here −I ₂
is given by the following equation. V ₂ =−I ₂ ·Z _L (3) When the voltage V ₂ at the output terminal 2 is given by the above equation (3), the voltage V ₁ at the input terminal 1 is given by the following equation. V ₁ =V ₂ +V _BE (4) That is, the voltage V ₁ is the voltage V ₂ plus the base-emitter voltage V _BE of the transistor 5. Here, if the voltage V _BE is sufficiently smaller than the voltage V ₂ , it is safe to assume that the voltage V ₁ is equal to V ₂ . Based on this condition, the transfer determinant corresponding to the above equation (1) is obtained from the above equations (2) and (4) as follows (5)
The formula is obtained. In the above equation (5), A≠0, D≠0, and B=C=0, which matches the definition of the impedance conversion circuit shown in the above equation (1). The impedance conversion circuit according to the embodiment shown in FIG. 2 is represented by a block diagram in FIG. This circuit of FIG. 3 is equivalent to the one in which one potential of the four-terminal circuit network in FIG. 1 is shared as a low potential V _S. Therefore, according to the circuit of FIG. 2, an input impedance proportional to the impedance of the load circuit 4 connected to the output terminal 2 can be obtained. Furthermore, by setting the value of the emitter resistor 9, the current transfer ratio γ ₁ of the current mirror circuit 6 can be changed to change the value of the output current I ₂ , so that desired impedance conversion characteristics can be provided. In order to examine the operating characteristics of the circuit of the embodiment shown in FIG. 2, a circuit as shown in FIG. 4 was formed and an experiment was conducted. In the figure, a pulse voltage source V _io is connected to an input terminal 1 via an input resistor R having a resistance value of 1 kΩ. Further, as a load circuit connected to the output terminal 2, a capacitor C having a capacitance value of 0.1 μF is connected. Furthermore, when the input PNP transistor 5 is integrated, it has a lateral structure and has a small current amplification factor, so that the collector current and emitter current do not match. In the circuit shown in FIG. 4, an input circuit 23 consisting of a combination of a pnp transistor 21 and an npn transistor 22 is used instead of the input pnp transistor 5. That is, in this input circuit 23 ,
The emitter of the pnp transistor 21 and the collector of the npn transistor 22
The collector of the pnp transistor 21 and the base of the npn transistor 22 are connected to each other, the common connection point of the emitter of the pnp transistor 21 and the collector of the npn transistor 22 is input terminal 1, the base of the pnp transistor 21 is connected to the output terminal 2, and the emitter of are connected to the collectors of the input side npn transistors 7 constituting the current mirror circuit 6 , respectively. In the input circuit 23 having such a configuration, the npn transistor 2 with a sufficiently large current amplification factor is used.
2 causes a current approximately equal to the input current value to flow from the emitter to input terminal 1, and also between input terminal 1 and output terminal 2 when input current is flowing to input terminal 1. The potential difference is made to match the base-emitter voltage V _BE of the pnp transistor 21, as in the case of the circuit shown in FIG. When a capacitor C is used as a load, a diode 24 is connected between the base and emitter of the pnp transistor 21 with the polarity shown in the figure in order to discharge the charge stored in the capacitor C. In the impedance conversion circuit configured in this manner, the capacitor C, which is a load, is charged when the pulse voltage source _Vio rises, and is discharged via the diode 24 when it falls. In this circuit, the input impedance Z _io seen from the input terminal 1 is given by the following equation (6). Z _io =1/jωC/γ ₁・γ ₂ …(6) Here, the two
Since the emitter areas of the npn transistors 7 and 8 are set equal, and the output side npn transistor 8 is provided with an emitter resistor 9, the current transfer ratio γ ₁ of the current mirror circuit 6 has a value smaller than 1. . In addition, two pnp transistors 11 and 1 constituting another current mirror circuit 10
Since the emitter areas of the current mirror circuits 10 and 2 are set equally, the current transfer ratio γ ₂ of the current mirror circuit 10 is
becomes 1. Therefore, the apparent value of the capacitance C seen from the input terminal 1 is C/γ ₁ , which is larger than C, and the input impedance Z _io in the above equation (6) is as follows (7)
It is given by Eq. Z _io = 1/jωC/γ ₁ …(7) In other words, the circuit in Figure 4 is equivalent to the circuit in which γ ₁ (γ ₁ <1) times the capacitance γ ₁・C is connected when viewed from input terminal 1. , a large time constant can be obtained with a small capacitance C. Figure 5 shows the pulse voltage source V _io and the output voltage obtained at output terminal 2 of the circuit in Figure 4 when this is input.
6 is a waveform diagram showing the voltage waveform with respect to V ₂ , and FIG. 6 is _a waveform diagram showing the voltage waveform of τ _r , FIG. 2 is a characteristic diagram showing the change characteristics of the time constant at the rise and fall of the voltage V ₂ indicated by τ _f . 6th
As can be seen from the figure, as the value of the emitter resistor 9 is increased and the current transfer ratio γ ₁ is decreased, the voltage V ₂
The time constant τ _r at the rise of τ r increases sequentially. This is because, as described above, the apparent value of the capacitance C increases as the value of γ ₁ decreases, and the input impedance Z _io also increases accordingly. On the other hand, regarding the fall of voltage V ₂ ,
Since the capacitor C is discharged via the diode 24, the time constant τ _f at this time becomes a constant value expressed by the product of the capacitor C and the input resistance R. In other words, the value of input resistance R is 1kΩ, and the value of capacitance C is 1μF.
Therefore, t _r is 10 ⁻⁴ sec., or 0.1 msec. From the characteristic diagram in Figure 6, the apparent magnification M of the capacitance C
When calculating the value of the emitter resistor 9 and the current transfer ratio γ 1 in the current mirror circuit 6 , precise calculation is not possible because there is no proportional relationship between the value and the current transfer ratio γ ₁ , but the following equation generally holds true. M=τ _r /τ _f …(8) In principle, the magnification M in the above equation (8) is M
There is a relationship of = 1/γ ₁ . Here, in Fig. 6, when the value of the emitter resistor 9 is 100Ω, that is, 10 ² Ω, the value of M is found to be M≒6.3, and further 1kΩ,
When finding the value of M when the resistance is 10kΩ, M≒24,
M≒175. By increasing the value of the emitter resistor 9 in this manner, a large value can be realized as the multiplication factor C of the capacitance C. In other words, if the impedance conversion circuit shown in Fig. 2 is used, a smaller capacitance can be prepared in order to obtain a constant time constant, so this invention can be applied to devices that use relatively large capacitors, such as low-pass filters. If applied, the pattern area can be reduced and high integration can be achieved. FIG. 7 is a circuit diagram showing the configuration of another embodiment of the present invention. This embodiment circuit differs from the embodiment circuit shown in FIG. 2 _above in that in the circuit shown in FIG. but,
In this example circuit, the emitter area of the npn transistor 7 on the input side of the current mirror circuit 6 is
This is achieved by making it wider than the npn transistor 8. That is, in the circuit of FIG. 7, the emitter area of transistor 7 is set to twice that of transistor 8, thereby defining the value of γ ₁ to 0.5. Therefore, in this embodiment circuit, the value of the apparent capacitance C seen from the input terminal 1 is doubled. Note that this invention is not limited to the above-described embodiments, and various modifications are possible. For example, in the above embodiment, a case was explained in which the current transfer ratio γ ₁ of one current mirror circuit 6 is set to a value smaller than 1 in order to increase the value of the apparent load capacitance seen from the input terminal 1. The current transfer ratio γ ₂ of the other current mirror circuit 10 may be set to a value smaller than 1, or both may be set to a value smaller than 1. In other words, when it is desired to obtain a large time constant, the total current transfer ratio γ ₁ and γ ₂ of the two current mirror circuits 6 and 10 is
Each current transfer ratio γ ₁ and γ ₂ may be set so that γ 1 and γ 2 are smaller than 1. Furthermore, in the above embodiment, the case where the input impedance seen from the input terminal 1 is larger than the load impedance was explained, but this is because the total current transfer ratio γ ₁ and γ ₂ of the two current mirror circuits 6 and 10 is less than 1. By setting the values of γ 1 and γ 2 so that γ ₁ and γ ₂ have large values, an input impedance that is proportional to and smaller than the load impedance may be obtained. Furthermore, the load circuit 4 may be other than a capacitor. Furthermore, the conductivity type and potential relationship of each transistor may be reversed. [Effects of the Invention] As described above, according to the present invention, it is possible to provide an impedance conversion circuit that is optimal for integrated circuit integration, and in particular, an impedance conversion circuit that is suitable for handling current as an input signal.

[Brief explanation of drawings]

FIG. 1 is a circuit diagram of an impedance conversion circuit expressed as a four-terminal network, FIG. 2 is a circuit diagram of an impedance conversion circuit according to an embodiment of the present invention, and FIG. 4 is an experimental circuit diagram for confirming the operation of the embodiment circuit of FIG. 2, FIG. 5 is a waveform diagram showing voltage waveforms in each part of the circuit of FIG. 4, and FIG. FIG. 4 is a characteristic diagram showing the characteristics of the circuit, and FIG. 7 is a circuit diagram showing another embodiment of the present invention. 1... Input terminal, 2... Output terminal, 3... Input current source, 4... Load circuit, 5... PNP transistor for input, 6, 10... Current mirror circuit, 7, 8, 2
2...npn transistor, 9...emitter resistor, 1
1, 12, 21...pnp transistor, 23...input circuit, 24...diode, _Vio ...pulse voltage source,
R...Input resistance, C...Capacitance.

Claims (1)

[Claims] 1. An input terminal, an output terminal, and a first to third
A first terminal is connected to the input terminal, a second terminal is connected to the output terminal, and the second terminal outputs a voltage corresponding to the voltage applied to the first terminal. At the same time, an input circuit outputs a current corresponding to the current input to the first terminal from the third terminal, and a current output from the third terminal of the input circuit is input and the current is proportional to this current. A first current mirror circuit that flows the current into the output side of the first current mirror circuit, and a current that is flown into the output side of the first current mirror circuit is inputted, and a current proportional to this current flows out from the output side.The output side is the above-mentioned output terminal. and a second current mirror circuit connected to the impedance conversion circuit. 2. The impedance conversion circuit according to claim 1, wherein the input circuit is a pnp transistor element having an emitter, a base, and a collector as first, second, and third terminals. 3 The input circuit includes an npn transistor element and a pnp
The common connection point between the collector of the npn transistor element and the emitter of the pnp transistor element is the first terminal, the base of the pnp transistor element is the second terminal, and the emitter of the npn transistor element is the third terminal. 2. The impedance conversion circuit according to claim 1, wherein the terminal of the pnp transistor element is connected to the base of the npn transistor element. 4. A current transfer ratio of the first and second current mirror circuits is set to 1 or less or 1 or more according to the ratio of the input current of the first current mirror circuit to the output current of the second current mirror circuit. An impedance conversion circuit according to claim 1.