JPS643088B2 - - Google Patents
Info
- Publication number
- JPS643088B2 JPS643088B2 JP13428684A JP13428684A JPS643088B2 JP S643088 B2 JPS643088 B2 JP S643088B2 JP 13428684 A JP13428684 A JP 13428684A JP 13428684 A JP13428684 A JP 13428684A JP S643088 B2 JPS643088 B2 JP S643088B2
- Authority
- JP
- Japan
- Prior art keywords
- ultrasonic
- ultrasonic delay
- buffer amplifier
- line
- delay
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired
Links
- 238000006243 chemical reaction Methods 0.000 claims description 6
- 230000003321 amplification Effects 0.000 description 2
- 230000003111 delayed effect Effects 0.000 description 2
- 238000010586 diagram Methods 0.000 description 2
- 238000003199 nucleic acid amplification method Methods 0.000 description 2
- 230000000694 effects Effects 0.000 description 1
- 239000011521 glass Substances 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03H—IMPEDANCE NETWORKS, e.g. RESONANT CIRCUITS; RESONATORS
- H03H9/00—Networks comprising electromechanical or electro-acoustic devices; Electromechanical resonators
- H03H9/30—Time-delay networks
Landscapes
- Physics & Mathematics (AREA)
- Acoustics & Sound (AREA)
- Piezo-Electric Or Mechanical Vibrators, Or Delay Or Filter Circuits (AREA)
Description
【発明の詳細な説明】
本発明は、超音波遅延線を使用した超音波遅延
回路を無調整化し、コストの安価な小型遅延回路
を得ることを目的とする。DETAILED DESCRIPTION OF THE INVENTION An object of the present invention is to eliminate the need for adjustment in an ultrasonic delay circuit using an ultrasonic delay line, and to obtain a small, inexpensive delay circuit.
超音波遅延線は、電気信号を一定時間遅延させ
るためのもので、音波の速度が電磁波のそれを約
10万分の１であることに着目して、電気信号をい
つたん超音波信号に変換し、数10μsecから数
100μsecの遅延時間を得た後、再び電気信号に変
換するものである。 Ultrasonic delay lines are used to delay electrical signals for a certain period of time, and the speed of sound waves is approximately equal to that of electromagnetic waves.
Focusing on the fact that it is 1/100,000th, we convert electrical signals into ultrasonic signals and convert them from several tens of microseconds to several tens of microseconds.
After obtaining a delay time of 100 μsec, it is converted back into an electrical signal.
第１図は、通常よく使用される超音波遅延線の
原理を示している。すなわち、ガラス遅延媒体１
の端面には電極２ａ，２ｂと２a′，２b′を設けた
電気−機械エネルギー変換機能をもつ変換素子３
と３′が取付けられており、いま、変換素子３の
電極２ａと２ｂ間に電気信号Eiが印加されると、
変換素子３はその信号の周波数に応じて機械振動
し、遅延媒体１中に超音波が放射される。この超
音波は遅延媒体１内を第１図に示す経路のように
多数回の反射をして、他端の変換素子３′に到達
し、これによつて変換素子３′が機械的に振動し
て、その超音波に応じた電気信号Epを電極２a′と
２b′間に発生する。 FIG. 1 shows the principle of a commonly used ultrasonic delay line. That is, glass retardation medium 1
A conversion element 3 having an electro-mechanical energy conversion function is provided with electrodes 2a, 2b and 2a', 2b' on the end face.
and 3' are attached, and now when an electric signal E i is applied between electrodes 2a and 2b of the conversion element 3,
The conversion element 3 mechanically vibrates according to the frequency of the signal, and ultrasonic waves are radiated into the delay medium 1. This ultrasonic wave is reflected many times within the delay medium 1 as shown in FIG. Then, an electric signal E p corresponding to the ultrasonic wave is generated between electrodes 2a' and 2b'.
本発明はこのような超音波遅延線を使用し、無
調整でもつて実質的に小型の超音波遅延回路を提
供しようとするものである。 The present invention uses such an ultrasonic delay line to provide a substantially compact ultrasonic delay circuit without adjustment.
以下、本発明の一実施例について第２図及び第
３図イ，ロ，ハとともに説明する。第２図におい
て、４は超音波遅延線であり、通常４端子である
が、入力端の２端子のみを使用し、この入力端に
返つてくる２次反射を利用するものである。すな
わち、上記超音波遅延線４は通常入力端に信号を
印加すると出力端より所定の遅延時間1τが得られ
るものであつて、本考案のような構成にした場
合、入力端には2τの遅延時間を有する反射波電圧
Ｅ（2τ）が出現するものである。そして、上記超
音波遅延線４の入力端にはエミツタフオロア等の
バツフアアンプ５が接続されており、このアンプ
５の増幅率は１である。上記バツフアアンプ５の
入力側、出力側からはライン６，７が取出されて
おり、それぞれ逆相になるようになつている。こ
の回路の出力は、上記ライン６，７が合流したラ
イン８により取出される。 An embodiment of the present invention will be described below with reference to FIGS. 2 and 3, A, B, and C. In FIG. 2, reference numeral 4 denotes an ultrasonic delay line, which normally has four terminals, but only the two input terminals are used, and the secondary reflection that returns to this input terminal is utilized. That is, the ultrasonic delay line 4 normally provides a predetermined delay time of 1τ from the output end when a signal is applied to the input end, but when configured as in the present invention, a delay of 2τ is obtained at the input end. A reflected wave voltage E(2τ) with time appears. A buffer amplifier 5 such as an emitter follower is connected to the input end of the ultrasonic delay line 4, and the amplification factor of this amplifier 5 is 1. Lines 6 and 7 are taken out from the input and output sides of the buffer amplifier 5, and are designed to have opposite phases. The output of this circuit is taken out through a line 8 where the lines 6 and 7 are joined.
つぎに、本発明回路の動作について説明する。
いま、本発明の回路にE1なる信号電圧が印加さ
れると、ライン６には第３図イの波形Ａに示すよ
うに−E1の電圧が現われる。一方、超音波遅延
線４の入力端の電圧、すなわちライン７に現われ
る電圧は、バツフアアンプ５の増幅率が１である
ので、第３図ロに示すようにE1の波形Ｂと、超
音波遅延線４の入力端に反射されてくる２次の不
要反射電圧Ｅ（2τ）の波形ｃである。すると出力
ライン８においては、波形Ａの−E1と波形Ｂの
E1は打ち消し合つて第３図ハに示すように波形
ＣのＥ（2τ）、すなわち遅延信号のみが得られる。 Next, the operation of the circuit of the present invention will be explained.
Now, when a signal voltage E 1 is applied to the circuit of the present invention, a voltage -E 1 appears on line 6 as shown in waveform A in FIG. 3A. On the other hand, since the amplification factor of the buffer amplifier 5 is 1, the voltage at the input end of the ultrasonic delay line 4, that is, the voltage appearing on the line 7, has a waveform B of E1 and an ultrasonic delay waveform, as shown in FIG. This is the waveform c of the secondary unnecessary reflected voltage E(2τ) reflected at the input end of the line 4. Then, on output line 8, -E 1 of waveform A and waveform B
E1 cancel each other out, and only E(2τ) of waveform C, that is, a delayed signal, is obtained as shown in FIG. 3C.
本発明の超音波遅延回路によれば、超音波遅延
線の２次の不要反射を利用できるため、超音波遅
延線自体を小型化できる。また、本発明の最大の
効果は、超音波遅延線の入力インピーダンス、２
次に不要反射量等に全く関係なく印加信号電圧
E1がキヤンセルされるので、無調整で遅延信号
が得られることである。このように本発明は、簡
単な構成でもつてコストの安価な小型遅延回路を
得ることができる。 According to the ultrasonic delay circuit of the present invention, unnecessary second-order reflections of the ultrasonic delay line can be utilized, so that the ultrasonic delay line itself can be miniaturized. Moreover, the greatest effect of the present invention is that the input impedance of the ultrasonic delay line, 2
Next, the applied signal voltage is applied regardless of the amount of unnecessary reflection, etc.
Since E1 is canceled, a delayed signal can be obtained without any adjustment. In this manner, the present invention can provide a small delay circuit with a simple configuration and low cost.
第１図は超音波遅延線の構成、動作を説明する
ための正面図、第２図は本発明に係る超音波遅延
回路の一実施例を示すブロツク図、第３図イ，
ロ，ハは第２図の回路における要部の電圧波形図
である。
４…超音波遅延線、５…バツフアアンプ。
FIG. 1 is a front view for explaining the configuration and operation of the ultrasonic delay line, FIG. 2 is a block diagram showing an embodiment of the ultrasonic delay circuit according to the present invention, and FIG.
B and C are voltage waveform diagrams of main parts in the circuit of FIG. 2. 4...Ultrasonic delay line, 5...Buffer amplifier.
Claims (1)
有する変換素子を取付けた構造をもつ超音波遅延
線の２次の遅延時間が出現する入力端にエミツタ
フオロア等のバツフアアンプを接続し、このバツ
フアアンプの入力側及び出力側をそれぞれ反対の
位相にして接続し、前記バツフアアンプの出力端
より出力を取出す構成としたことを特徴とする超
音波遅延回路。1. A buffer amplifier such as an emitter follower is connected to the input end where the secondary delay time of an ultrasonic delay line has a structure in which a conversion element having an electro-mechanical energy conversion function is attached to a delay medium, and the input side of this buffer amplifier and An ultrasonic delay circuit characterized in that the output sides are connected in opposite phases, and the output is taken out from the output end of the buffer amplifier.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP13428684A JPS6022820A (en) | 1984-06-28 | 1984-06-28 | Ultrasonic wave delay circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP13428684A JPS6022820A (en) | 1984-06-28 | 1984-06-28 | Ultrasonic wave delay circuit |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS6022820A JPS6022820A (en) | 1985-02-05 |
| JPS643088B2 true JPS643088B2 (en) | 1989-01-19 |
Family
ID=15124728
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP13428684A Granted JPS6022820A (en) | 1984-06-28 | 1984-06-28 | Ultrasonic wave delay circuit |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS6022820A (en) |
-
1984
- 1984-06-28 JP JP13428684A patent/JPS6022820A/en active Granted
Also Published As
| Publication number | Publication date |
|---|---|
| JPS6022820A (en) | 1985-02-05 |
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