JPS6427720U - - Google Patents
Info
- Publication number
- JPS6427720U JPS6427720U JP12057687U JP12057687U JPS6427720U JP S6427720 U JPS6427720 U JP S6427720U JP 12057687 U JP12057687 U JP 12057687U JP 12057687 U JP12057687 U JP 12057687U JP S6427720 U JPS6427720 U JP S6427720U
- Authority
- JP
- Japan
- Prior art keywords
- register
- control bus
- interface circuit
- controlling
- bus interface
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000010586 diagram Methods 0.000 description 2
Landscapes
- Techniques For Improving Reliability Of Storages (AREA)
- Power Sources (AREA)
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP12057687U JPS6427720U (fi) | 1987-08-06 | 1987-08-06 |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP12057687U JPS6427720U (fi) | 1987-08-06 | 1987-08-06 |
Publications (1)
Publication Number | Publication Date |
---|---|
JPS6427720U true JPS6427720U (fi) | 1989-02-17 |
Family
ID=31366811
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP12057687U Pending JPS6427720U (fi) | 1987-08-06 | 1987-08-06 |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS6427720U (fi) |
-
1987
- 1987-08-06 JP JP12057687U patent/JPS6427720U/ja active Pending
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