JPS6425242A - High quality system in automatic logical circuit conversion - Google Patents

High quality system in automatic logical circuit conversion

Info

Publication number
JPS6425242A
JPS6425242A JP62182715A JP18271587A JPS6425242A JP S6425242 A JPS6425242 A JP S6425242A JP 62182715 A JP62182715 A JP 62182715A JP 18271587 A JP18271587 A JP 18271587A JP S6425242 A JPS6425242 A JP S6425242A
Authority
JP
Japan
Prior art keywords
rule
logical circuit
matching
competition
evaluation function
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP62182715A
Other languages
Japanese (ja)
Inventor
Atsushi Ishikawa
Masanobu Hiramine
Kozo Ishida
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Mitsubishi Electric Corp
Original Assignee
Mitsubishi Electric Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Mitsubishi Electric Corp filed Critical Mitsubishi Electric Corp
Priority to JP62182715A priority Critical patent/JPS6425242A/en
Publication of JPS6425242A publication Critical patent/JPS6425242A/en
Pending legal-status Critical Current

Links

Abstract

PURPOSE:To obtain a high quality converting circuit comparable to that in the available design and to realize a logical circuit automatic conversion by introducing an evaluation function to change a value dynamically to a competition cancelling means in accordance with circuit data to obtain a matching. CONSTITUTION:A logical circuit converting part 1 is composed of a working memory 2, an IF-THEN form rule base 3 and an interpreter 4. A matching means 5 executes a pattern matching between the logical circuit data of the memory 2 and the rule conditions of the rule base 3. A competition cancelling means 6 uses the evaluation function out of the competition set which is the set of the rule to succeed in the matching and selects one rule. A rule executing means 7 updates the logical circuit data of the memory 2 in accordance with the executing part of the selected rule. The evaluation function value is calculated considering the number of cells to be allocated, an effective utilization factor and the number of element steps.
JP62182715A 1987-07-21 1987-07-21 High quality system in automatic logical circuit conversion Pending JPS6425242A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP62182715A JPS6425242A (en) 1987-07-21 1987-07-21 High quality system in automatic logical circuit conversion

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP62182715A JPS6425242A (en) 1987-07-21 1987-07-21 High quality system in automatic logical circuit conversion

Publications (1)

Publication Number Publication Date
JPS6425242A true JPS6425242A (en) 1989-01-27

Family

ID=16123170

Family Applications (1)

Application Number Title Priority Date Filing Date
JP62182715A Pending JPS6425242A (en) 1987-07-21 1987-07-21 High quality system in automatic logical circuit conversion

Country Status (1)

Country Link
JP (1) JPS6425242A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH03269631A (en) * 1990-03-19 1991-12-02 Fujitsu Ltd Constitution processing system for rule base system
JPH07295818A (en) * 1994-04-26 1995-11-10 Nec Corp Rule processor

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH03269631A (en) * 1990-03-19 1991-12-02 Fujitsu Ltd Constitution processing system for rule base system
JPH07295818A (en) * 1994-04-26 1995-11-10 Nec Corp Rule processor

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