JPS6424855U - - Google Patents

Info

Publication number
JPS6424855U
JPS6424855U JP1987120551U JP12055187U JPS6424855U JP S6424855 U JPS6424855 U JP S6424855U JP 1987120551 U JP1987120551 U JP 1987120551U JP 12055187 U JP12055187 U JP 12055187U JP S6424855 U JPS6424855 U JP S6424855U
Authority
JP
Japan
Prior art keywords
mount
lead
integrated circuit
semiconductor integrated
stitches
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP1987120551U
Other languages
English (en)
Japanese (ja)
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed filed Critical
Priority to JP1987120551U priority Critical patent/JPS6424855U/ja
Publication of JPS6424855U publication Critical patent/JPS6424855U/ja
Pending legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10WGENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00Interconnections or connectors in packages
    • H10W72/851Dispositions of multiple connectors or interconnections
    • H10W72/874On different surfaces
    • H10W72/884Die-attach connectors and bond wires
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10WGENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00Package configurations
    • H10W90/701Package configurations characterised by the relative positions of pads or connectors relative to package parts
    • H10W90/751Package configurations characterised by the relative positions of pads or connectors relative to package parts of bond wires
    • H10W90/756Package configurations characterised by the relative positions of pads or connectors relative to package parts of bond wires between a chip and a stacked lead frame, conducting package substrate or heat sink

Landscapes

  • Lead Frames For Integrated Circuits (AREA)
JP1987120551U 1987-08-05 1987-08-05 Pending JPS6424855U (enFirst)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP1987120551U JPS6424855U (enFirst) 1987-08-05 1987-08-05

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP1987120551U JPS6424855U (enFirst) 1987-08-05 1987-08-05

Publications (1)

Publication Number Publication Date
JPS6424855U true JPS6424855U (enFirst) 1989-02-10

Family

ID=31366761

Family Applications (1)

Application Number Title Priority Date Filing Date
JP1987120551U Pending JPS6424855U (enFirst) 1987-08-05 1987-08-05

Country Status (1)

Country Link
JP (1) JPS6424855U (enFirst)

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