JPS6424503U - - Google Patents

Description

[Brief explanation of the drawing]

FIG. 1 is a circuit configuration diagram showing an erase current control circuit in a flexible disk drive device that is an embodiment of this invention, and FIG. 2 is a circuit configuration diagram showing an erase current control circuit in a conventional flexible disk drive device. Figure 3 is the second
3 is a timing chart showing currents at various parts in the erase current control circuit shown in the figure. In the figure, 1...Write gate (WRITE
GATE) signal, 2a...On delay/off delay timer (ON DELAY/OFF D
ELAY TIMER) circuit, 2b...first time constant circuit, 2c, 2d...second time constant circuit, 3
...Erase current drive (ERASE DRI)
VE) circuit, 4... erase head (ERASE
HEAD), 4a...first erase head (
S0), 4b...Second erase head (S1)
, 5...selection (SELECT) signal, 6... selection (SELECT) circuit. In addition, in the figures, the same reference numerals indicate the same or equivalent parts.

Claims (1)

[Scope of utility model registration request] an on-delay timer circuit operated by a write gate signal and controlled by a first time constant circuit; and an off-delay timer circuit operated by the write gate signal and controlled by a second time constant circuit. an off-delay timer circuit, a time constant variable adjustment means provided in one or both of the first time constant circuit and the second time constant circuit, and the on-delay/on-delay timer circuit;
A flexible disk drive device comprising an erase current drive circuit that controls an on-delay time and an off-delay time of an erase current using timing generated by an off-delay timer circuit.