JPS6423888U - - Google Patents
Info
- Publication number
- JPS6423888U JPS6423888U JP11789187U JP11789187U JPS6423888U JP S6423888 U JPS6423888 U JP S6423888U JP 11789187 U JP11789187 U JP 11789187U JP 11789187 U JP11789187 U JP 11789187U JP S6423888 U JPS6423888 U JP S6423888U
- Authority
- JP
- Japan
- Prior art keywords
- turned
- time
- circuit
- opening
- input terminal
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000010586 diagram Methods 0.000 description 2
- 238000001514 detection method Methods 0.000 description 1
- 239000004973 liquid crystal related substance Substances 0.000 description 1
- 230000010355 oscillation Effects 0.000 description 1
Landscapes
- Details Of Connecting Devices For Male And Female Coupling (AREA)
Description
第１図は本考案の一実施例の外観をそれに接続
するプラグと共に示す図、第２図は上記実施例の
ブロツク回路図である。
１……コンセント、２……オスプラグ、３……
メスプラグ、４……キーボード、５……液晶表示
パネル、１０……プラグ、１０ａ……オスプラグ
、１１……発振回路、１２……分周回路、１３…
…計時計数回路、１４……表示制御部、１５……
表示部、１６……キー入力部、１７……選択カウ
ンタ、１８，１９，２０……バスコントロールゲ
ート、２１……第１記憶回路、２２……第２記憶
回路、２３……第３記憶回路、２４，２５，２６
……一致検出回路、２７，２８，２９……ワンシ
ヨツト回路、３０，３１，３２……スイツチ制御
回路、３３，３４，３５……リレー、３６……電
源回路。
FIG. 1 is a diagram showing the appearance of an embodiment of the present invention together with a plug connected thereto, and FIG. 2 is a block circuit diagram of the embodiment. 1...Outlet, 2...Male plug, 3...
Female plug, 4... Keyboard, 5... Liquid crystal display panel, 10... Plug, 10a... Male plug, 11... Oscillation circuit, 12... Frequency dividing circuit, 13...
...Counting circuit, 14...Display control section, 15...
Display section, 16... Key input section, 17... Selection counter, 18, 19, 20... Bus control gate, 21... First memory circuit, 22... Second memory circuit, 23... Third memory circuit , 24, 25, 26
... Coincidence detection circuit, 27, 28, 29 ... One shot circuit, 30, 31, 32 ... Switch control circuit, 33, 34, 35 ... Relay, 36 ... Power supply circuit.
Claims (1)
オフする複数の開閉手段と、 上記複数の開閉手段について、それぞれ、オン
する時刻およびオフする時刻を記憶する記憶手段
と、 上記記憶手段の記憶に基づいて、上記複数の開
閉手段の各々を、そのオン又はオフする時刻に到
つたときオン又はオフする制御手段とを備えたこ
とを特徴とするコンセント。[Scope of claim for utility model registration] A single input terminal connected to a power source, a plurality of output terminals connected to an electrical appliance, and each connection between the input terminal and each output terminal
a plurality of opening/closing means to be turned off; a storage means for storing a time when each of the plurality of opening/closing means is to be turned on and a time to be turned off; An outlet characterized by comprising a control means that turns on or off when the time to turn on or off comes.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP11789187U JPS6423888U (en) | 1987-07-31 | 1987-07-31 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP11789187U JPS6423888U (en) | 1987-07-31 | 1987-07-31 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS6423888U true JPS6423888U (en) | 1989-02-08 |
Family
ID=31361749
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP11789187U Pending JPS6423888U (en) | 1987-07-31 | 1987-07-31 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS6423888U (en) |
-
1987
- 1987-07-31 JP JP11789187U patent/JPS6423888U/ja active Pending
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