JPS6423188U - - Google Patents
Info
- Publication number
- JPS6423188U JPS6423188U JP11752287U JP11752287U JPS6423188U JP S6423188 U JPS6423188 U JP S6423188U JP 11752287 U JP11752287 U JP 11752287U JP 11752287 U JP11752287 U JP 11752287U JP S6423188 U JPS6423188 U JP S6423188U
- Authority
- JP
- Japan
- Prior art keywords
- signal
- output
- adder
- video signal
- delay means
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000000926 separation method Methods 0.000 claims description 6
- 230000001934 delay Effects 0.000 claims 2
- 239000000284 extract Substances 0.000 claims 1
- 238000010586 diagram Methods 0.000 description 2
Landscapes
- Processing Of Color Television Signals (AREA)
Description
第１図はこの考案に係る回路が適用されたＹ／
Ｃ分離回路の概要を示すブロツク図、第２図は従
来のＹ／Ｃ分離回路を示すブロツク図である。
１……Ｙ／Ｃ分離回路、２……第１の遅延手段
、３……インバータ、４……第１の加算器、５…
…第２の遅延手段、６……デイレイライン、７…
…移相器、８……第２の加算器、Ａ……映像信号
、Ｃ……色信号、Ｙ……輝度信号。
Figure 1 shows the Y/R to which the circuit according to this invention is applied.
FIG. 2 is a block diagram showing an outline of a C separation circuit, and FIG. 2 is a block diagram showing a conventional Y/C separation circuit. DESCRIPTION OF SYMBOLS 1... Y/C separation circuit, 2... First delay means, 3... Inverter, 4... First adder, 5...
...Second delay means, 6...Delay line, 7...
... Phase shifter, 8... Second adder, A... Video signal, C... Color signal, Y... Luminance signal.
Claims (1)
から輝度信号と色信号を分離するＹ／Ｃ分離回路
において、 上記映像信号を少なくとも１水平走査期間だけ
遅延する第１の遅延手段と、 上記映像信号を少なくとも１水平走査期間だけ
遅延する周波数帯域の広い第２の遅延手段と、 上記第１の遅延手段の入出力信号から色信号を
抽出分離する第１の加算器と、 上記第２の遅延手段より出力された映像信号と
上記第１の加算器出力から輝度信号を抽出分離す
る第２の加算器を備え、 上記第２の遅延手段の出力映像信号が上記第１
の加算器出力と丁度１水平走査期間の時間差を有
するように上記第２の遅延手段の遅延時間が選定
されてなることを特徴とするＹ／Ｃ分離回路。[Claims for Utility Model Registration] In a Y/C separation circuit that separates a luminance signal and a chrominance signal from a video signal in which a chrominance signal is frequency-multiplexed on a luminance signal, a first Y/C separation circuit that delays the video signal by at least one horizontal scanning period; a second delay means with a wide frequency band that delays the video signal by at least one horizontal scanning period; and a first adder that extracts and separates a color signal from the input/output signal of the first delay means. and a second adder for extracting and separating a luminance signal from the video signal output from the second delay means and the output of the first adder, wherein the output video signal of the second delay means is the output video signal of the first adder. 1
A Y/C separation circuit characterized in that the delay time of the second delay means is selected so as to have a time difference of exactly one horizontal scanning period from the adder output.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP11752287U JPS6423188U (en) | 1987-07-31 | 1987-07-31 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP11752287U JPS6423188U (en) | 1987-07-31 | 1987-07-31 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS6423188U true JPS6423188U (en) | 1989-02-07 |
Family
ID=31361052
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP11752287U Pending JPS6423188U (en) | 1987-07-31 | 1987-07-31 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS6423188U (en) |
-
1987
- 1987-07-31 JP JP11752287U patent/JPS6423188U/ja active Pending
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