JPS642275B2 - - Google Patents

Description

[Detailed Description of the Invention] [Field of Application of the Invention] The present invention relates to a magnetic recording/reproducing device, for example, a video signal
Regarding a rotary two-head video tape recorder that records in the width direction of a magnetic tape using two rotating magnetic heads and reproduces the device signals using the same head, in detail, the two magnetic heads are alternately switched to reproduce video signals. This invention relates to improvements in circuits that generate signals that enable recording/reproduction and pseudo vertical synchronization signals.

[Prior art]

Figure 1 is a block diagram of a conventional head switching signal generation circuit for a rotating two-head video tape recorder.
FIG. 2 is a diagram showing the output waveform of the main part.

In FIG. 1, reference numerals 10 and 20 indicate magnetic heads for alternately recording or reproducing video signals on the magnetic tape 4 for each field. These two magnetic heads 1
0 and 20 are mounted on the disk 3 at an angle of 180 degrees to each other, and rotated together with the disk 3 at a constant speed by the disk motor 2. Two magnets 11 and 21 are attached to the disk 3 at an angle of 180° to each other in relation to the positions of the magnetic heads 10 and 20, and these are detected by the storage head 1. From the output H from the tack head 1, a signal H1 whose position is detected in relation to the magnet 11 and a signal H2 whose position is detected in relation to the magnet 21 are generated.
are separated and outputted by the separation amplification circuit 5. Output signals H1 and H2 from circuit 5 are supplied to delay multi-circuits 6 and 7, respectively, and are individually delayed. 8 is an R/S flip-flop circuit, whose output Q is triggered (set) by the output A1 from the delay multi-circuit 6 to a high level "H".
Then, it is triggered (reset) by the output A2 from the delay multi circuit 7 and becomes a low level "L". The output Q from this circuit 8 is outputted from a terminal 200 as a head switching signal. The phase of the magnetic head 10 is defined by the rising phase of this head switching signal Q, and the phase of the magnetic head 20 is defined by the falling phase of the signal Q. Since the position of the magnetic heads 10 and 20 and the magnet 1 are detected,
It is necessary to adjust the phase of the signal Q according to the relative mounting position of the tack head 1, 21, and 1, and therefore, conventionally, it has been necessary to individually adjust the phase using the delay multicircuits 6 and 7.

In addition, the head switching signal Q is used as a reference signal for the head disk servo system in order to correctly record the video signal at a specified position on the magnetic tape 4 during recording, and is used as a reference signal for the head disk servo system to correctly record the video signal at a specified position on the magnetic tape 4. It is used to correctly switch the video signals that are played back alternately, so if the above phase adjustment is insufficient, normal recording and playback will not be performed, noise will appear in the playback image, and compatible playback will be difficult. Problems such as becoming For this reason, the delay multicircuits 6 and 7 are designed so that the spatial relative positions of the magnetic heads 10 and 20 and the magnetic tape 4 become a prescribed function, and so that the duty ratio of the head switching signal Q becomes exactly 50%. , each needs to be finely adjusted individually,
The adjustment procedure is complicated, which increases the time required for adjustment and increases the cost of the set. In Fig. 2, are pseudo synchronization signals, B ₁ , B ₂
is the output signal of the delay multi-circuits 6 and 7. On the other hand, in this rotating two-head type VTR, there is a function for playing back the tape 4 recorded at the standard tape speed by running it at a speed different from the standard speed, for example, at a speed higher than the standard speed. Some VTRs employ special playback functions, such as running the tape for high-speed (quick viewing) playback, or stopping tape 4 and playing it still. In this special playback function, the magnetic heads 10 and 20 cross over and trace a plurality of recorded tracks (not shown), so that the reproduced video signal is partially corrupted by noise. If the vertical synchronization signal portion of the signal is corrupted by noise, the vertical deflection of the TY receiver will be disturbed, causing the problem that the reproduced image will be vertically unstable.

In order to solve this problem, conventionally, a so-called pseudo vertical synchronizing signal V (V in Fig. 2), which is formed into a pulse with a predetermined pulse width by appropriately delaying the phase from the rising and falling edges of the above-mentioned head switching signal Q, is regenerated. A method of inserting it into the video signal is adopted.

However, even in this case, the adjustment of the delay multi-circuits 6 and 7 may be insufficient, or the circuits 6 and 7 may be insufficiently adjusted due to fluctuations in power supply voltage, changes in ambient temperature and humidity, etc.
There is a problem in that when the delay time of the image changes, the phase of the pseudo vertical synchronization signal changes, causing vertical image fluctuation.

In addition, a so-called 8mm video is being considered as a new standard VTR, but in this VTR, the heads 10 and 20 simultaneously scan the tape 4, recording time-base compressed audio signals in the so-called overlap area, or New proposals have been made, such as recording a pilot signal necessary for controlling the posture of the heads 10, 20 during recording in this overlap area when performing reproduction tracking by perturbing the heads 10, 20. but,
In this case, although not shown, in addition to the delay multicircuits 6 and 7, two separate delay multicircuits triggered by H1 and H2 are required, and their respective outputs (B ₁ and B ₂ in Fig. 2) are required. ), a method of specifying the recording position of each signal to be recorded in the above-mentioned overlap area is required. Therefore, such new
VCRs have had the problem of increasing the number of peripheral circuits and circuit adjustments, making it difficult to make the device smaller and lower in cost.

Furthermore, when integrating this head switching signal forming circuit into an IC, in the conventional example described above, the input circuit is complex and there are many adjustment circuits, so the number of pins required for the IC increases, making it difficult to achieve large scale and high integration. There were problems such as difficulty in realizing the

[Purpose of the invention]

The purpose of the present invention is to provide standard playback mode, high speed playback,
It is an object of the present invention to provide a magnetic recording and reproducing device that can always perform stable reproduction in a special reproduction mode such as static reproduction.

[Summary of the invention]

In the present invention, a predetermined clock is counted based on a signal detected once per rotation in synchronization with the rotation of the magnetic head, and the counting time is always equal to 1/2 of the rotation period of the magnetic head. The count value is determined based on the count output, and a signal that is time-leading than the desired head switching signal is obtained, and a pseudo vertical synchronization signal is generated so that it is delayed by a predetermined phase and has a predetermined pulse width. It is something that forms.

[Embodiments of the invention]

DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of a head switching signal and pseudo vertical synchronization signal forming circuit according to the present invention will be described below with reference to the drawings.

FIG. 3 is a diagram showing an embodiment of a head disk servo system during reproduction that is constructed using a head switching signal and pseudo vertical synchronization signal forming circuit 60 according to the present invention, and FIG. FIGS. 5 and 6 are waveform diagrams illustrating an embodiment of the switching signal and pseudo vertical synchronization signal forming circuit 60 for explaining its operation.

In FIG. 3, a magnetic head 1 is attached to a disk 3.
0 and 20 are attached at an angle of 180 degrees to each other, and one magnet 11 is attached in relation to the position of the magnetic head 10, the position of which is detected by the tack head 1. The output from the task head 1 is supplied to an amplifier circuit 42 and amplified. The output H1 (H1 in FIG. 5) is supplied to the delay multi-circuit 43, and the circuit 43 supplies the delay multi-circuit 43 so that the spatial relative positions of the magnetic head 10 and the magnetic tape 4 are in a prescribed relationship.
The phase is adjusted by . The output A1 of the circuit 43 (A1 in FIG. 5) is supplied to the head switching signal forming circuit 60. In this circuit 60, as will be described later, a time T ₀ (fifth
After T ₀ ) in FIG. 5, the head switching signal Q ₃ (Q ₃ in FIG. 5) is “H” for a time T equal to 1/2 of the rotation period of the magnetic heads 10, 20 and then “L”. Formed and output. This signal Q ₃ is supplied to one side of the phase comparator circuit 40 . The other side of the circuit 40 is supplied with the reference signal from the reference signal generating circuit 30, and the circuit 40 outputs a signal corresponding to the phase difference between the head switching signal _Q3 and the reference signal. The output from this circuit 40 is supplied to the disk motor 2 via a disk servo circuit 41. Circuits 42, 43, 60, 40, 4 including disk motor 2
1 constitutes a negative feedback control system, and is controlled so that the rotational speed of the disk motor 2 and the frequency of the head switching signal _Q3 are equal to the frequency of the reference signal from the circuit 30. The circuit 50 is a data generation circuit, and generates and outputs n-bit binary data _D1 and m-bit binary data _D2 to be supplied to the circuit 60 and the circuit 30, respectively.
The circuit 30 is composed of an m-bit counter. Then, the clock CP ₂ from the terminal 31 is counted, that is, the number of times equal to the value of the m-bit binary data D ₂ from the circuit 50 is repeatedly counted to obtain a predetermined frequency f.
generates a reference signal. The head switching signal _Q3 from the circuit 60 is supplied to the reproduced video signal circuit 300 and is used to switch the video signals alternately reproduced field by field from the magnetic heads 10 and 20 into one continuous signal. .

The circuit 60 is a circuit for generating a head switching signal _Q3 and a pseudo vertical synchronizing signal V necessary for executing the above special reproduction function. Reference numeral 310 denotes an adder circuit which adds the pseudo vertical synchronizing signal V from the circuit 300 to the reproduced video signal from the reproduced video circuit 300 and leads them to the terminal 320.

Next, the operation of the head switching signal and pseudo vertical synchronizing signal generating circuit 60 will be explained based on the embodiment shown in FIG.

In FIG. 4, 61 is an input terminal of the clock CP1, 62 is an input terminal of the output A1 from the delay multi-circuit 43 of FIG. 6, and 63 is an input terminal of the data generation circuit 50.
65 is the output terminal for the head switching signal _Q3 , 67 is the output terminal for the pseudo vertical synchronization signal V, and 66 is the mode designation signal M.
This is the input terminal of 70 is a clock clutch circuit, 77 is a delay multi circuit, 71 to 76 are R/S
Flip-flop (hereinafter abbreviated as FF), 80
is an inverter, 81-96 are OR gates, 90-
101 is an AND gate, and 110 is an n-bit counter. Decoders 111 to 113 decode the count value of the counter 110, and the decoders 111 and 112 output "H" when the count value of the counter 110 reaches _N0 and _N2, respectively, and the decoder 113 decodes the count value of the counter 110. counting data D ₀
and the data D ₁ from the input terminal 63, and when they match, that is, when the count value of the counter 110 becomes equal to the value N ₁ of the data D ₁ , the signal becomes “H”.
Output.

Here, N ₀ and N ₂ are both determined to be smaller than N ₁ (N ₀ , N ₂ <N ₁ ), and if the frequency of clock CP ₁ is f ₁ , the counting time of N ₀ of counter 110 is T. The counting time T ₁ for ₀ and N ₁ and the counting time T ₂ for N ₂ are given by the following equations, respectively.

T ₀ =N ₀ /f ₁ …(1) T ₁ =N ₁ /f ₁ …(2) T ₂ =N ₂ /f ₁ …(3) T=T ₀ /T ₁ …(4) Also, the above The value of N ₀ and the value of N ₁ (value of data D ₁ ) are determined so as to satisfy the following formula in each mode described below.

T=1/2f...(5) Here, f is as mentioned above. Circuit 3 in Figure 3
is the frequency of the reference signal from 0, and its frequency f
is determined by data D ₂ from circuit 50.

That is, in the first playback mode in which the data is played back by running at the same standard speed as when recording, the value of the data _D2 is determined so that the frequency f of the reference signal is approximately equal to the frame frequency _f0 of the video signal. ,Also
The values of N ₀ and N ₁ (value of data D ₁ ) are determined to satisfy the above equation (5).

Furthermore, even in the second playback mode in which the magnetic tape 4 is run at a speed different from the standard speed for special playback such as high-speed or static playback, the data D ₁ , D ₂ and N ₀ are processed so as to satisfy the above formula 5. , N ₁ is determined.

In this second playback mode, the relative speed determined by the rotation speed of the magnetic heads 10 and 20 and the running speed of the magnetic tape 4 is different from that during recording, so the horizontal scanning frequency of the playback video signal is different from the normal frequency. Offset occurs, and as a result, horizontal synchronization of the TV receiver cannot be maintained, resulting in so-called out-of-synchronization, or a time difference occurs between the luminance signal and the color signal, resulting in color shift. In order to solve this problem, it is necessary to give a certain deviation to the rotational speeds of the magnetic heads 10 and 20 to eliminate the offset in the horizontal scanning frequency of the reproduced video signal. For example, in this second reproduction mode, if the deviation value of the rotational frequency to be given to the rotational speed of the magnetic heads 10 and 20 is Δf, then the frequency f of the reference signal from the reference signal generation circuit 30 is f=f ₀ +
The value of data D ₂ is determined so that △f, and according to this, N ₀ and N ₁ (value of data D ₁ ) are determined so that the above T becomes T = 1/2 (f ₀ + △f). is determined.

That is, specifically, from the above equations (1) to (5), in the first reproduction mode, N ₀ +N ₁ =f ₁ /2f ₀ ...(6) In the second reproduction mode, N ₀ +N ₁ =f ₁ /2(f ₀ +△f) (7) The value N ₁ of the data D ₁ is set so as to satisfy the following.

The mode designation signal M input to the terminal 66 is "L" in the first reproduction mode and "H" in the second reproduction mode.

Next, the operation of the circuit shown in FIG. 4 will be explained. First, the operation in the first reproduction mode will be explained using the waveform diagram of FIG. In the first reproduction mode, the mode designation signal M from the terminal 66 is "L", so the gates 90, 94, 8, and 101 are closed, and no pseudo vertical synchronization signal is output from the terminal 67. The FFs 75 and 76, the delay multiplexer 77, and the decoder 112 are involved in forming the pseudo vertical synchronizing signal V, and since the pseudo vertical synchronizing signal is unnecessary in this first reproduction mode, the operation thereof will be omitted. The signal A ₁ (A ₁ in FIG. 5) from the terminal 62 is supplied to the clock clutch circuit 70 via the gate 81, and from the falling edge of the signal A ₁ , the pulse P ₁ (A 1 in FIG. 5) synchronized with the clock CP ₁ from the terminal 61 is generated. P ₁ ) in Figure 5 is generated and output. F.F71 is set by signal _A1 , and since gate 90 is closed, F.F.
71 is never reset, and its _Q0 output is always "H". Output P ₁ from circuit 70
is supplied to the set input S of FF72, the set input S of FF73 via gate 91, and the reset input R of FF74 via gate 83.
Q ₁ output of 72 (Q ₁ in Figure 5) is “H”, FF73
The Q ₂ output (Q ₂ in Figure 5) of FF74 is “H”, _{the 2} output is “L”, the Q ₃ output of FF74 (Q ₃ in Figure 5) is “L”, and _{the 3} output is “H”. . When the _Q1 output of FF72 becomes “H”, the gate 95 opens and the terminal 61
The clock CP ₁ from 1 is input to the clock input C of the counter 110, and the counter 110 starts counting from a count value of zero. Count value of counter 110 is N ₀
When this happens, the output from the decoder 111 becomes "H", the _Q2 output of FF73 becomes "H", and _{the 3rd} output of FF74 becomes "H", so the output of the gate 97 becomes "H", and therefore FF74 is set and its output becomes "H". output
Q ₃ becomes “H”, ₃ output becomes “L”, gate 9
7 is closed. On the other hand, “H” from gate 97
The output is supplied to the reset input terminal R of the counter 110 via the gate 84, and the counter 110 is reset so that its count value becomes zero, and at the same time, the output of the decoder 111 becomes "L". counter 11
0 continues counting from the count value zero, and when the count value matches the value _N1 of the data _D1 from the terminal 63, the decoder 113 outputs "H". The FF73 is reset by the "H" output from this decoder 113, and its output _Q2 is "L" and _Q2 is "H".
becomes. Also, “H” from this decoder 113
The output is sent to the counter 110 via gates 85 and 84.
is supplied to the reset input terminal R of the counter 11.
0 is reset again and the count value becomes zero,
At the same time, the output of the decoder 113 becomes "L". The counter 110 continues counting again from the count value zero, and when the count value reaches _N0 again, the decoder 1
11 outputs "H", and ₂ of FF73 is "H", so the gate 96 is opened and its output is "H".Furthermore, since the output of the inverter 80 is "H", the gate 93 is also opened and its output is "H". Therefore, the FF 72 is reset through the gate 82, its output _Q2 becomes "L", the gate 95 is closed, and the counting operation of the counter 110 is stopped.
On the other hand, the "H" output from gate 96 is output from gate 84.
is supplied to the counter 110 via the counter 1
10 is reset and its count value becomes zero, and at the same time the output of decoder 111 becomes "L". Furthermore, the “H” output from this gate 96
Reset input terminal R of FF74 via 9 and 83
The output _Q3 becomes "L".

The output Q ₃ of this FF 74 is outputted from a terminal 65 as a head switching signal Q ₃ . The period during which the head switching signal Q ₃ is "H" is equal to the period T (=T ₁ +T ₀ ) during which the counter 110 counts (N ₁ +N ₀ ), and the output Q ₂ of the FF 73 is "H". The period is also equal to the period T (=T ₀ +T ₁ ) in which the counter 110 counts (N ₀ +N ₁ ), and this output
As is clear from FIG. 5, Q ₂ is a signal that precedes the head switching signal Q ₃ by exactly a time T ₀ (hereinafter referred to as the preceding signal Q ₂ ).

Next, the operation in the second reproduction mode will be explained using the waveform diagram of FIG. 6.

In the second reproduction mode, the mode designation signal M is "H" and the output of the inverter 80 is "L", so gates 93 and 99 are closed. The FF 71 is set by the signal A ₁ from the terminal 62, and its output Q ₀ (Q ₀ in FIG. 6) becomes "H". The FFs 72 and 73 are set by the pulse P ₁ generated by the circuit 70 at the fall of the signal A ₁ , and the FF 74 is reset, so that the respective outputs Q ₁ and Q ₂ are "H" and Q ₃ is "L". ”, the counter 110 is supplied with a clock and starts counting, and after counting _N0 , the decoder 111 outputs “H”, which sets the FF 74 through the gate 97, and its output
_Q3 becomes "H", F.F75 is also set, and its output _Q4 ( _Q4 in FIG. 6) also becomes "H". At the same time, the counter 110 is reset via the gate 84, its count value becomes zero, and the output of the decoder 111 becomes "L". The above operation is exactly the same as in the first reproduction mode.

The counter 110 continues counting, and when the count reaches _N2 , the output from the decoder 112 becomes "H", _Q3 of FF74 goes "H", and _Q4 of FF75 goes to "H".
is "H", the gate 100 is opened and its output becomes "H", so F.F75 is reset and its output _Q4 becomes "L". During the period when the output _Q4 of the FF75 is “H”, the counter 110 is
It is equal to the period T ₂ (formula (3) above) during which N ₂ is counted.

The counter 110 continues to count, and the counted value is
When it reaches _N1 , the output from the datar 113 becomes "H", thereby resetting the F.F 73 and its output _Q2 changes from "H" to "L". At the same time, FF 72 is also reset via gates 85, 94, and 82, and its direction _Q1 becomes "L", and gate 95
is closed, the counter 110 stops counting, and the counter 110 is also reset via the gates 85 and 84, so that the counted value becomes zero, and the output of the decoder 113 becomes "L". On the other hand, the above FF
The output Q ₂ of 73 is input to the delay multi-circuit 77,
Pulse (with pulse width T ₀ ′) triggered by the falling edge of Q ₂ from “H” to “L” and delayed by time T ₀ ′
A ₃ (A ₃ in FIG. 6) is output from the circuit 77. This pulse _A3 is supplied to the reset input terminal R of the FF 71 through the gate 90, and its output _Q0 becomes "L" and _Q0 becomes "H". Further, pulse A ₃ is supplied to the circuit 70 via gates 90 and 81,
As in the case of A ₁ , the pulse starts from the falling edge of pulse A ₃ .
P ₁ is formed and output.

By the output P ₁ from this circuit 70, F.F72
is set, the output _Q1 becomes "H" again, the gate 95 opens, and the counter 110 restarts counting from zero. On the other hand, this pulse P ₁ resets the FF 74 via the gate 83 and its output Q ₃ becomes “L”, and also causes the output Q ₅ (the FF 74 set via the gate 92 Figure 6
_Q5 ) becomes “H”. When the count value of the counter 110 reaches _N2 , the output of the decoder 112 becomes “H” again.
Therefore, since FF73 ₂ is “H”, gate 9
8 opens and its output becomes “H”, which causes
FF76 is reset and its output _Q5 is “L”
becomes. At the same time, the counter 110 is reset via the gates 85 and 84, the count value becomes zero, and the output of the decoder 112 becomes "L". The period during which the output Q ₅ of the FF 76 is "H" is equal to T ₂ similarly to the output Q ₄ of the FF 7 described above. The output Q ₄ of these FF75 and the output Q ₅ of FF76 are added at gate 86 and sent to pseudo vertical synchronization signal V via gate 101.
(V in FIG. 6) is output from the terminal 67.

In the second playback mode described above, the output _Q2 of the FF73 precedes the head switching signal _Q3 , which is the output of the FF74, by a time _T0 , as in the first playback mode. The period during which the signal Q ₂ is "H" is equal to T. Furthermore, as is clear from FIG. 6, the pseudo vertical synchronization signal V can be regarded as being formed from this preceding signal _Q2 , and specifically, the rising edge of the preceding signal _Q2 ,
_{Pseudo vertical synchronizing} signal V
is formed.

The output head switching signal Q ₃ is thus formed.
In both the first and second modes, the phase of the preceding signal _Q2 is synchronized with the reference signal from the reference signal generation circuit 30 by the negative feedback control operation of the head disk servo system, so its frequency is the same as the reference signal. Since T is determined so as to be equal to the frequency f of the signal and to satisfy the above formula 5, its duty ratio is always 50%.

In addition, in the second playback mode, when T ₀ = T ₀ ', the duty ratio of the head switching signal Q ₃ is 50%.
Although it does not cause any problems, it does not cause any problems.

In this way, the duty ratio of the head switching signal _Q3 and the preceding signal _Q2 is exactly 50%, so that stable reproduction can be performed. Furthermore, compared to the conventional method shown in FIG. 1, the number of phase adjustment circuits for forming the head switching signal can be reduced by one.

In addition, in order to perform various special playbacks such as high-speed playback, low-speed playback, or static playback, it is necessary to change the phase of the pseudo vertical synchronization signal depending on the value of the so-called H arrangement _αH and the track trace conditions of the magnetic head. Therefore, it is necessary to take a large phase adjustment allowance, but as mentioned above, the pseudo vertical synchronizing signal V is a signal that precedes the head switching signal _Q3 in time.
Q ₂ , the phase adjustment margin (T ₀ ' in Figure 6) can be made sufficiently larger than the conventional method shown in Figure 2, and the number of phase adjustment circuits required can be reduced to one. be able to. In addition, since the duty ratio of this preceding signal _Q2 is always 50% as mentioned above, the desired pseudo vertical synchronization signal can be stably obtained without phase fluctuations, and the reproduced image can be stabilized without vertical fluctuation. It is possible to provide a device that can perform playback and is compatible with a wide variety of playback modes.

Although the embodiment shown in FIG. 4 shows the case where the value of N ₀ is the same in the first and second modes, the present invention is not limited to this;
The second and second N ₀ may be different.

Further, in the embodiment of FIG. 4, the delay multi-circuit 77
We have shown a case in which the phase of _one of the pseudo vertical synchronization signals (FF76 output Q ₅ ) can be adjusted using For example, although not shown, a counter 110 may be used in parallel, and the counter 1 is counted during the period from the end of N ₁ counting until the start of the next N ₂ counting (period T ₀ ' in FIG. 6).
Continuously count 10 by N ₀ ′ (=T ₀ ′f ₁ ),
At the end of counting N ₀ ', set FF76,
The desired output _Q5 may be obtained by resetting the FF 76 upon completion of the subsequent counting of _N2 . The embodiment shown in FIG. 4 is a case where two types of pseudo vertical synchronization signals Q ₄ and Q ₅ , which have different phases and repeat at two field periods, are formed individually, and are an example of application in high-speed or static playback. However, the present invention is not limited to this; for example, even in a mode in which playback is performed at 1/2 speed of the standard speed, which requires four types of pseudo vertical synchronization signals that are repeated at four field cycles, one of them can be implemented. The output Q ₄ shown in the example is generated digitally with a fixed phase, and the other three are output Q ₅ shown in the example, generated digitally with a fixed phase.
A desired pseudo vertical synchronization signal can be formed by individually adjusting the phase of each of the three delay multicircuits and operating them cyclically.

Furthermore, in the embodiment shown in FIG. 3, the head disk servo system is configured with a so-called phase control system, and the frequency of the reference signal from the reference signal generation circuit 30 is changed in each mode. However, at least in the second mode, the head disk servo system is configured only with a speed control system, and the speed control gives a predetermined deviation to the rotational speed of the magnetic head, and only the forming circuit 60' is configured with the head disk servo system as a speed control system. It is also possible to supply data _D1 according to the deviation.

The effects obtained in any of the above cases are the same, and do not depart from the spirit of the present invention.

〔Effect of the invention〕

According to the present invention, it is possible to always generate a head switching signal with a duty ratio of 50%, or a preceding signal with a duty ratio of 50% that is ahead of the head switching signal in time.Moreover, since it is generated digitally, it is possible to generate a head switching signal with an extremely high precision and a power supply. Stable operation can always be obtained without being affected by voltage fluctuations, changes in ambient temperature and humidity, etc.

[Brief explanation of drawings]

Figure 1 is a block diagram of a conventional head switching signal generation circuit, Figure 2 is a waveform diagram for explaining its operation, and Figure 3 is a waveform diagram for explaining its operation.
FIG. 4 is a block diagram showing an embodiment of the head switching signal generation circuit according to the invention, and FIGS. 5 and 6 are waveform diagrams for explaining its operation. be.

Claims (1)

[Scope of Claims] 1. A magnetic recording and reproducing apparatus that records and reproduces video signals on a magnetic tape using two rotating magnetic heads, including a detection circuit that detects the rotational phase of one of the magnetic heads, and a detection circuit that detects the rotational phase of one of the magnetic heads; A first counting operation starts counting with the output from the circuit and counts the clock signal by a predetermined value _N0 , followed by a set value _N1.
counter means including a counter that performs a second counting operation, and the continuously counted value (N ₀ +N ₁ ) of the counter is configured to adjust the frequency of the clock so that the output signal of the rotational phase detection circuit is constant. means for setting the value _N1 to be approximately equal to a value divided by a frequency equal to twice the number of rotations of the magnetic head, which is determined by speed control such that the number of rotations is equal to the frequency;
means for delaying the output based on the completion of the second counting for a predetermined period of time; a signal generation means for forming a pseudo vertical synchronization signal of the above and a second pseudo vertical synchronization signal based on the output from the delay means; and a tape on which the first and second pseudo vertical synchronization signals are recorded. 1. A magnetic recording and reproducing device, characterized in that it is provided with means for inserting into a video signal that is reproduced at a high speed. 2. The counter means further includes a decoder for decoding a predetermined value _N2 of the count of the counter subsequent to the end of the first counting, and a counting operation of the counter based on the output from the delay means to obtain the above value.
A third counting operation of counting N ₂ is performed, and the signal generation means generates a leading edge of each of the first pseudo vertical synchronization signals by the output based on the end of the first counting and the output of the decoder. and a trailing edge of the second pseudo vertical synchronization signal, and the output from the delay means and the output based on the completion of the third counting form a leading edge and a trailing edge, respectively, of the second pseudo vertical synchronization signal. A magnetic recording and reproducing apparatus according to claim 1, characterized in that: 3. The signal generating means includes means for forming a head switching signal for alternately switching the video signal reproduced by the rotating magnetic head, and the output based on the completion of the first counting and the output of the delay means. 3. A magnetic recording and reproducing apparatus as claimed in claim 1 or 2, characterized in that a head switching signal whose state is sequentially inverted is formed. 4. having means for generating a reference signal and means for synchronizing the rotational phase of the magnetic head with the reference signal;
Claim 1 or Claim 1, characterized in that the frequency of the reference signal is set so that the relative speed between the tape and the magnetic head is approximately the same as that during recording, depending on the playback speed of the tape. The magnetic recording and reproducing device according to item 2 or 3.