JPS642167U - - Google Patents
Info
- Publication number
- JPS642167U JPS642167U JP9629687U JP9629687U JPS642167U JP S642167 U JPS642167 U JP S642167U JP 9629687 U JP9629687 U JP 9629687U JP 9629687 U JP9629687 U JP 9629687U JP S642167 U JPS642167 U JP S642167U
- Authority
- JP
- Japan
- Prior art keywords
- time axis
- observation device
- logic signal
- waveform observation
- line
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000010586 diagram Methods 0.000 description 1
Landscapes
- Tests Of Electronic Circuits (AREA)
Description
第１図：本考案に係る波形観測装置のブロツク
回路図、第２図：同装置における表示部のパター
ンを示す正面図、第３図：使用状態における同表
示部の正面図、第４図：同装置の外観正面図。
尚図面中、１：波形観測装置、２，３：時間軸
表示ライン、４：表示部、Ｓ：ロジツク信号。
Figure 1: Block circuit diagram of the waveform observation device according to the present invention, Figure 2: Front view showing the pattern of the display section of the device, Figure 3: Front view of the display section in use, Figure 4: FIG. 2 is an external front view of the device. In the drawing, 1: waveform observation device, 2, 3: time axis display line, 4: display section, S: logic signal.
Claims (1)
レベルの時間軸をそれぞれ表示する一対の平行に
離間した時間軸表示ラインを有する表示部を備え
、各時間軸表示ラインによつて前記ロジツク信号
を表示することを特徴とする波形観測装置。 (2) 前記時間軸表示ラインはドツト形式で構成
したことを特徴とする実用新案登録請求の範囲第
１項記載の波形観測装置。[Claims for Utility Model Registration] (1) A display section having a pair of parallel and spaced apart time axis display lines each displaying a low level time axis and a high level time axis of a logic signal; A waveform observation device characterized in that the logic signal is displayed by a line. (2) The waveform observation device according to claim 1, wherein the time axis display line is configured in a dot format.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP9629687U JPS642167U (en) | 1987-06-23 | 1987-06-23 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP9629687U JPS642167U (en) | 1987-06-23 | 1987-06-23 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS642167U true JPS642167U (en) | 1989-01-09 |
Family
ID=30961879
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP9629687U Pending JPS642167U (en) | 1987-06-23 | 1987-06-23 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS642167U (en) |
Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5023798A (en) * | 1973-06-30 | 1975-03-14 | ||
| JPS5462870A (en) * | 1977-10-28 | 1979-05-21 | Kazutoyo Iwamatsu | Method of indicating time series of logic signal |
-
1987
- 1987-06-23 JP JP9629687U patent/JPS642167U/ja active Pending
Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5023798A (en) * | 1973-06-30 | 1975-03-14 | ||
| JPS5462870A (en) * | 1977-10-28 | 1979-05-21 | Kazutoyo Iwamatsu | Method of indicating time series of logic signal |
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