JPS6421637A - Communication system between microprocessor and memory or peripheral lsi - Google Patents

Communication system between microprocessor and memory or peripheral lsi

Info

Publication number
JPS6421637A
JPS6421637A JP62179527A JP17952787A JPS6421637A JP S6421637 A JPS6421637 A JP S6421637A JP 62179527 A JP62179527 A JP 62179527A JP 17952787 A JP17952787 A JP 17952787A JP S6421637 A JPS6421637 A JP S6421637A
Authority
JP
Japan
Prior art keywords
memory
microprocessor
encipherment
data
access area
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP62179527A
Other languages
Japanese (ja)
Inventor
Mitsuhiro Azuma
Naoya Torii
Ryota Akiyama
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to JP62179527A priority Critical patent/JPS6421637A/en
Publication of JPS6421637A publication Critical patent/JPS6421637A/en
Pending legal-status Critical Current

Links

Landscapes

  • Storage Device Security (AREA)

Abstract

PURPOSE:To make encipherment of a data between a processor and a memory to be secured by using an access area identification means provided to a microprocessor chip so as to identify a designation area via an address bus and selecting a route via a cryptographic/decoding circuit. CONSTITUTION:Based on an address via an address bus, an access area identification means of a microprocessor chip 10 identifies whether an access area is a peripheral LSI 3 or a memory 2. In case of the memory 2 as the result of identification, a switch is changed over, an encipherment/decode circuit 5 is interposed between the microprocessor 1 and the memory 2 to form a route. As a result, the data between the microprocessor and the memory is made encipherment to secure the data in an excellent way.
JP62179527A 1987-07-17 1987-07-17 Communication system between microprocessor and memory or peripheral lsi Pending JPS6421637A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP62179527A JPS6421637A (en) 1987-07-17 1987-07-17 Communication system between microprocessor and memory or peripheral lsi

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP62179527A JPS6421637A (en) 1987-07-17 1987-07-17 Communication system between microprocessor and memory or peripheral lsi

Publications (1)

Publication Number Publication Date
JPS6421637A true JPS6421637A (en) 1989-01-25

Family

ID=16067318

Family Applications (1)

Application Number Title Priority Date Filing Date
JP62179527A Pending JPS6421637A (en) 1987-07-17 1987-07-17 Communication system between microprocessor and memory or peripheral lsi

Country Status (1)

Country Link
JP (1) JPS6421637A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2004252978A (en) * 2003-02-18 2004-09-09 Micronas Gmbh Processor provided with external storage device
US9305183B2 (en) 2000-06-30 2016-04-05 Intel Corporation Method and apparatus for secure execution using a secure memory partition

Cited By (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US9305183B2 (en) 2000-06-30 2016-04-05 Intel Corporation Method and apparatus for secure execution using a secure memory partition
US9323954B2 (en) 2000-06-30 2016-04-26 Intel Corporation Method and apparatus for secure execution using a secure memory partition
US9507963B2 (en) 2000-06-30 2016-11-29 Intel Corporation Method and apparatus for secure execution using a secure memory partition
US9507962B2 (en) 2000-06-30 2016-11-29 Intel Corporation Method and apparatus for secure execution using a secure memory partition
US9547779B2 (en) 2000-06-30 2017-01-17 Intel Corporation Method and apparatus for secure execution using a secure memory partition
US9619672B2 (en) 2000-06-30 2017-04-11 Intel Corporation Method and apparatus for secure execution using a secure memory partition
US9971909B2 (en) 2000-06-30 2018-05-15 Intel Corporation Method and apparatus for secure execution using a secure memory partition
US10572689B2 (en) 2000-06-30 2020-02-25 Intel Corporation Method and apparatus for secure execution using a secure memory partition
JP2004252978A (en) * 2003-02-18 2004-09-09 Micronas Gmbh Processor provided with external storage device

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