JPS641982B2 - - Google Patents

Info

Publication number
JPS641982B2
JPS641982B2 JP7742180A JP7742180A JPS641982B2 JP S641982 B2 JPS641982 B2 JP S641982B2 JP 7742180 A JP7742180 A JP 7742180A JP 7742180 A JP7742180 A JP 7742180A JP S641982 B2 JPS641982 B2 JP S641982B2
Authority
JP
Japan
Prior art keywords
equalizer
circuit
output
evaluation value
input
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired
Application number
JP7742180A
Other languages
Japanese (ja)
Other versions
JPS573440A (en
Inventor
Fumio Akashi
Kojiro Watanabe
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
Nippon Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Nippon Electric Co Ltd filed Critical Nippon Electric Co Ltd
Priority to JP7742180A priority Critical patent/JPS573440A/en
Publication of JPS573440A publication Critical patent/JPS573440A/en
Publication of JPS641982B2 publication Critical patent/JPS641982B2/ja
Granted legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H04ELECTRIC COMMUNICATION TECHNIQUE
    • H04LTRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L25/00Baseband systems
    • H04L25/02Details ; arrangements for supplying electrical power along data transmission lines
    • H04L25/03Shaping networks in transmitter or receiver, e.g. adaptive shaping networks
    • H04L25/03006Arrangements for removing intersymbol interference
    • H04L25/03012Arrangements for removing intersymbol interference operating in the time domain
    • H04L25/03019Arrangements for removing intersymbol interference operating in the time domain adaptive, i.e. capable of adjustment during data reception
    • H04L25/03038Arrangements for removing intersymbol interference operating in the time domain adaptive, i.e. capable of adjustment during data reception with a non-recursive structure

Landscapes

  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Computer Networks & Wireless Communication (AREA)
  • Signal Processing (AREA)
  • Filters That Use Time-Delay Elements (AREA)
  • Dc Digital Transmission (AREA)
  • Cable Transmission Systems, Equalization Of Radio And Reduction Of Echo (AREA)

Description

【発明の詳細な説明】 本発明は多相多値変調に用いる適応等化器に関
するものである。
DETAILED DESCRIPTION OF THE INVENTION The present invention relates to an adaptive equalizer used in polyphase multilevel modulation.

多相多値変調の適応等化器においては、初期符
号間干渉が多い場合、等化器出力において判定を
行なつても、正確な判定がほとんど不可能であ
り、判定結果を用いた等化器の修正が正しく行な
えないという問題がある。
In an adaptive equalizer for multi-phase multilevel modulation, if there is a lot of initial intersymbol interference, it is almost impossible to make an accurate judgment even if the judgment is made at the equalizer output, and equalization using the judgment result is difficult. There is a problem that the device cannot be corrected correctly.

本発明の目的は、従来の送信シンボルに対応し
た判定方法を用いないで、新しい判定方法を用い
る事により、初期符号間干渉が大きくても収束が
可能な等化器を提供する。
An object of the present invention is to provide an equalizer that can converge even if initial intersymbol interference is large, by using a new determination method instead of the conventional determination method corresponding to transmitted symbols.

以下に、CCITTV・29で勧告された多相多値
変調を例に本発明を説明する。
The present invention will be explained below using the polyphase multilevel modulation recommended by CCITTV-29 as an example.

多相多値変調の2系列の復調波形は、その同
相、直交両成分を2軸とした2次元平面上の軌跡
として表わされる。ここで用いた例では各シンボ
ルは第1図に示した2次元平面で(a1〜a16)で
表わされ配置をもつている。これに対して一定円
周内で分布する様な符号間干渉b1〜b16を考える。
中心点付近においては様々な方向からの符号間干
渉が互に交錯している為にほとんど正しい判定が
不可能である。しかしながら外側レベルの方を観
察すると、8相のシンボルがほとんど正しく判別
しうる事がわかる。従つて、円Cの外側に受信波
形が配置された時のみ、すなわち受信波形の振幅
値(第1図では原点からの距離)が、第1図の円
Cの半径より大である時のみ、8相の判定を行な
えば、8相の誤まりの少ない判定が可能であるの
で、この判定結果を用いて適応等化器の修正を行
なえば容易に収束に達しうる。
The two series of demodulated waveforms of multi-phase multi-level modulation are expressed as trajectories on a two-dimensional plane with both in-phase and orthogonal components as two axes. In the example used here, each symbol is represented by (a 1 to a 16 ) on the two-dimensional plane shown in FIG. 1 and has an arrangement. On the other hand, let us consider intersymbol interference b 1 to b 16 that is distributed within a constant circumference.
In the vicinity of the center point, intersymbol interference from various directions intersect with each other, making it almost impossible to make a correct determination. However, if we look at the outer level, we can see that most of the eight-phase symbols can be correctly identified. Therefore, only when the received waveform is placed outside the circle C, that is, only when the amplitude value of the received waveform (distance from the origin in FIG. 1) is larger than the radius of the circle C in FIG. If 8-phase determination is performed, 8-phase determination with fewer errors is possible, so if the adaptive equalizer is modified using this determination result, convergence can be easily reached.

ここで円Cの外側か内側かの判定は直交および
同相信号の2乗和を計算し、これを円Cの半径の
2乗値として表わされる評価値と比較する事によ
つて表わされる。
Here, the determination as to whether the signal is outside or inside the circle C is expressed by calculating the square sum of the orthogonal and in-phase signals and comparing this with an evaluation value expressed as the square value of the radius of the circle C.

この発明は前記手段を用いた構成にて、引き込
み範囲の広い適応等化が可能となる特徴をもつて
いる。
The present invention has a feature that adaptive equalization with a wide pull-in range is possible with a configuration using the above-mentioned means.

以下に図面を用いて本発明の実施例を説明す
る。
Embodiments of the present invention will be described below with reference to the drawings.

第2図は本発明の実施例の全体を表わすブロツ
ク図である。端子1および2により入来した波形
は等化器3に入来する。等化器3の2系列の信号
はそれぞれ3つに分岐され評価値計算回路4に入
力し、計算された評価値を比較回路8に入力す
る。比較回路8では端子7から入力される一定振
幅値、すなわち第1図の円Cの半径と比較され計
算回路4からの入力が大きい場合には1′を、小
さい場合にはO′を判定回路5に出力する。判定
回路5においては、比較回路8からの入力が1′
の場合のみに、等化器3の出力に応じて多相変調
の判定を行ないその出力を修正回路6に入力す
る。修正回路6には、等化器3の出力およびその
内部状態も入力され、これらの信号から等化器3
の特性を変更する信号が出力される。この様な手
段を用いて適応的な等化がなされる。
FIG. 2 is a block diagram showing the entire embodiment of the present invention. The waveforms coming in via terminals 1 and 2 enter equalizer 3. The two series of signals from the equalizer 3 are each branched into three and input into an evaluation value calculation circuit 4, and the calculated evaluation value is input into a comparison circuit 8. Comparison circuit 8 compares the constant amplitude value input from terminal 7, that is, the radius of circle C in Figure 1, and determines 1' if the input from calculation circuit 4 is large, and O' if small Output to 5. In the determination circuit 5, the input from the comparison circuit 8 is 1'
Only in this case, polyphase modulation is determined according to the output of the equalizer 3 and the output thereof is input to the correction circuit 6. The output of the equalizer 3 and its internal state are also input to the correction circuit 6, and from these signals the equalizer 3
A signal is output that changes the characteristics of. Adaptive equalization is performed using such means.

第3図は計算回路4の更に詳しい実施例を示す
ブロツク図である。端子41,42からは等化器
出力が入来し、それぞれ2乗器43,44を介し
て加算器45で加え合わされる。この加え合わせ
た結果と一定値とを比較することにより第1図で
示した円Cの内側に受信波形があるか、外側にあ
るかの判定が可能となる。ここでは評価値として
2乗和を用いる場合の例であるが、絶対値和等他
の評価値を用いる事も可能である。
FIG. 3 is a block diagram showing a more detailed embodiment of the calculation circuit 4. Equalizer outputs enter from terminals 41 and 42 and are added together by an adder 45 via squarers 43 and 44, respectively. By comparing this addition result with a constant value, it is possible to determine whether the received waveform is inside or outside the circle C shown in FIG. Although the example here uses the sum of squares as the evaluation value, it is also possible to use other evaluation values such as the sum of absolute values.

第4図は等化器3として3タツプの2次元トラ
ンスバーサル型の等化器を用い、平均2乗和最小
基準によつて修正する場合の等化器3および修正
回路6を含んだ一実施例を示すブロツク図であ
る。端子1および2より入来した信号は、それぞ
れ遅延素子31,33および32,34に順次入
力される。各遅延素子の入出力から分岐した信号
は、複素掛算器35,36,37に入力される。
複素掛算器ではタツプゲイン入力との掛算が行な
われ、それぞれ2系列の出力が求められ、結果は
累算器38,39に入力し、累算器38および3
9で累算され等化出力が端子40,50に求ま
る。等化器3は遅延素子31,32,33,3
4、複素掛算器35,36,37累算器38,3
9よりなる。端子40,50に出力された等化器
出力は同時に誤差計算回路63に入力し、端子6
1,62より入力した判定出力との差が計算され
誤差信号が複素掛算器64,65,66に入力さ
れる。複素掛算器64,65,66にはそれぞれ
遅延素子より分岐された信号も入力し、複素掛算
が行なわれ、その出力は固定ゲイン回路67,6
8,69,70,71,72を介して積分器7
3,74,75,76,77,78に入力し、各
積分器出力に新しいタツプゲインを得る。修正回
路6は誤差計算回路63,複素掛算器64,6
5,66、固定ゲイン回路67,68,69,7
0,71,72、積分器73,74,75,7
6,77,78から構成される。またここで用い
られる複素掛算器35,36,37,64,6
5,66はすべて第5図に示す様な4つの掛算器
311,312,313,314と2つの加算器
315,316とからなる構成となつている。こ
こで述べたのは3タツプの2次元トランスバーサ
ル型に対して平均2乗和最小基準を用いて修正し
た場合であるが、他の形状の等化器および他の修
正回路を用いた構成も可能である。
FIG. 4 shows an implementation including the equalizer 3 and the correction circuit 6 in the case where a 3-tap two-dimensional transversal type equalizer is used as the equalizer 3, and correction is performed based on the minimum mean square sum criterion. FIG. 2 is a block diagram showing an example. Signals coming from terminals 1 and 2 are sequentially input to delay elements 31, 33 and 32, 34, respectively. Signals branched from the input and output of each delay element are input to complex multipliers 35, 36, and 37.
The complex multiplier performs multiplication with the tap gain input to obtain two series of outputs, and the results are input to accumulators 38 and 39.
9 and equalized outputs are obtained at terminals 40 and 50. Equalizer 3 includes delay elements 31, 32, 33, 3
4. Complex multipliers 35, 36, 37 accumulators 38, 3
Consists of 9. The equalizer outputs output to terminals 40 and 50 are simultaneously input to an error calculation circuit 63, and are output to terminal 6.
1 and 62 are calculated, and an error signal is input to complex multipliers 64, 65, and 66. The signals branched from the delay elements are also input to the complex multipliers 64, 65, and 66, respectively, and complex multiplication is performed, and the outputs are sent to the fixed gain circuits 67, 6.
Integrator 7 via 8, 69, 70, 71, 72
3, 74, 75, 76, 77, and 78 to obtain a new tap gain at each integrator output. The correction circuit 6 includes an error calculation circuit 63 and a complex multiplier 64, 6.
5, 66, fixed gain circuit 67, 68, 69, 7
0, 71, 72, integrator 73, 74, 75, 7
Consists of 6, 77, and 78. Also, the complex multipliers 35, 36, 37, 64, 6 used here
5 and 66 are all constructed of four multipliers 311, 312, 313, 314 and two adders 315, 316 as shown in FIG. The case described here is a case in which a three-tap two-dimensional transversal type is corrected using the minimum mean-squares criterion, but configurations using other shapes of equalizers and other correction circuits are also possible. It is possible.

以上述べた構成によつて、本発明は引込み範囲
の広い適応等化器を提供するものである。
With the configuration described above, the present invention provides an adaptive equalizer with a wide pull-in range.

【図面の簡単な説明】[Brief explanation of the drawing]

第1図は受信信号の軌跡を説明するために示す
2次元平面を表わす図、第2図は本発明の実施例
を示すブロツク図、第3図は評価値計算回路の実
施例を示すブロツク図、第4図は等化器および修
正回路の一実施例を示すブロツク図、第5図は複
素掛算器の一例を示すブロツク図である。 図において、3は等化器、4は評価値計算回
路、8は比較回路、5は判定回路、6は修正回
路、43,44,311,312,313,31
4は掛算器、45,315,316は加算器、3
1,32,33,34は遅延素子、35,36,
37,64,65,66は複素掛算器、38,3
9は累算器、63は誤差検出回路、67,68,
69,70,71,72は固定ゲイン回路、7
3,74,75,76,77,78は積分器であ
る。
FIG. 1 is a diagram showing a two-dimensional plane shown to explain the locus of a received signal, FIG. 2 is a block diagram showing an embodiment of the present invention, and FIG. 3 is a block diagram showing an embodiment of an evaluation value calculation circuit. , FIG. 4 is a block diagram showing one embodiment of the equalizer and correction circuit, and FIG. 5 is a block diagram showing an example of the complex multiplier. In the figure, 3 is an equalizer, 4 is an evaluation value calculation circuit, 8 is a comparison circuit, 5 is a judgment circuit, 6 is a correction circuit, 43, 44, 311, 312, 313, 31
4 is a multiplier, 45, 315, 316 is an adder, 3
1, 32, 33, 34 are delay elements, 35, 36,
37, 64, 65, 66 are complex multipliers, 38, 3
9 is an accumulator, 63 is an error detection circuit, 67, 68,
69, 70, 71, 72 are fixed gain circuits, 7
3, 74, 75, 76, 77, and 78 are integrators.

Claims (1)

【特許請求の範囲】[Claims] 1 多相多値変調データ伝送の受信機において、
復調後の2系列の信号を入力とし、2系列の信号
を出力する等化器と、該等化器の2系列の出力信
号より前記多相多値変調信号の振幅を示す評価値
を計算する評価値計算回路と、該評価値と一定の
振幅を示す値を比較する比較回路と、前記比較回
路の結果において評価値が一定値より大きい場合
にのみ該等化器出力信号に対して多相の判定を行
なう判定回路と、該判定回路出力、該等化器出力
と該等化器の内部信号とを用いて該等化器の特性
を適応的に変更する修正回路とを備えたことを特
徴とする適応等化器。
1 In a receiver for multi-phase multi-level modulation data transmission,
an equalizer that inputs demodulated two-series signals and outputs two-series signals; and calculates an evaluation value indicating the amplitude of the multiphase multilevel modulation signal from the two-series output signals of the equalizer. an evaluation value calculation circuit; a comparison circuit that compares the evaluation value with a value indicating a constant amplitude; and a correction circuit that adaptively changes the characteristics of the equalizer using the output of the determination circuit, the output of the equalizer, and the internal signal of the equalizer. Features an adaptive equalizer.
JP7742180A 1980-06-09 1980-06-09 Adaptive equalizer Granted JPS573440A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP7742180A JPS573440A (en) 1980-06-09 1980-06-09 Adaptive equalizer

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP7742180A JPS573440A (en) 1980-06-09 1980-06-09 Adaptive equalizer

Publications (2)

Publication Number Publication Date
JPS573440A JPS573440A (en) 1982-01-08
JPS641982B2 true JPS641982B2 (en) 1989-01-13

Family

ID=13633490

Family Applications (1)

Application Number Title Priority Date Filing Date
JP7742180A Granted JPS573440A (en) 1980-06-09 1980-06-09 Adaptive equalizer

Country Status (1)

Country Link
JP (1) JPS573440A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0483680U (en) * 1990-11-29 1992-07-21

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CA1181817A (en) * 1982-04-28 1985-01-29 John D. Mcnicol Intermediate frequency slope compensation control arrangements

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0483680U (en) * 1990-11-29 1992-07-21

Also Published As

Publication number Publication date
JPS573440A (en) 1982-01-08

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