JPS6415947U - - Google Patents

Info

Publication number
JPS6415947U
JPS6415947U JP10742687U JP10742687U JPS6415947U JP S6415947 U JPS6415947 U JP S6415947U JP 10742687 U JP10742687 U JP 10742687U JP 10742687 U JP10742687 U JP 10742687U JP S6415947 U JPS6415947 U JP S6415947U
Authority
JP
Japan
Prior art keywords
guide groove
color
comparator body
mounting table
plane
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP10742687U
Other languages
English (en)
Japanese (ja)
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed filed Critical
Priority to JP10742687U priority Critical patent/JPS6415947U/ja
Publication of JPS6415947U publication Critical patent/JPS6415947U/ja
Pending legal-status Critical Current

Links

Landscapes

  • Investigating Or Analyzing Non-Biological Materials By The Use Of Chemical Means (AREA)
  • Investigating Or Analysing Materials By The Use Of Chemical Reactions (AREA)
JP10742687U 1987-07-13 1987-07-13 Pending JPS6415947U (enrdf_load_stackoverflow)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP10742687U JPS6415947U (enrdf_load_stackoverflow) 1987-07-13 1987-07-13

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP10742687U JPS6415947U (enrdf_load_stackoverflow) 1987-07-13 1987-07-13

Publications (1)

Publication Number Publication Date
JPS6415947U true JPS6415947U (enrdf_load_stackoverflow) 1989-01-26

Family

ID=31341830

Family Applications (1)

Application Number Title Priority Date Filing Date
JP10742687U Pending JPS6415947U (enrdf_load_stackoverflow) 1987-07-13 1987-07-13

Country Status (1)

Country Link
JP (1) JPS6415947U (enrdf_load_stackoverflow)

Cited By (34)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6877146B1 (en) 2001-06-03 2005-04-05 Cadence Design Systems, Inc. Method and apparatus for routing a set of nets
US6892369B2 (en) 2002-11-18 2005-05-10 Cadence Design Systems, Inc. Method and apparatus for costing routes of nets
US6898773B1 (en) 2002-01-22 2005-05-24 Cadence Design Systems, Inc. Method and apparatus for producing multi-layer topological routes
US6915501B2 (en) 2001-01-19 2005-07-05 Cadence Design Systems, Inc. LP method and apparatus for identifying routes
US6938234B1 (en) 2002-01-22 2005-08-30 Cadence Design Systems, Inc. Method and apparatus for defining vias
US6944841B1 (en) 2002-01-22 2005-09-13 Cadence Design Systems, Inc. Method and apparatus for proportionate costing of vias
US6957408B1 (en) 2002-01-22 2005-10-18 Cadence Design Systems, Inc. Method and apparatus for routing nets in an integrated circuit layout
US6957411B1 (en) 2001-06-03 2005-10-18 Cadence Design Systems, Inc. Gridless IC layout and method and apparatus for generating such a layout
US6988257B2 (en) 2002-11-18 2006-01-17 Cadence Design Systems, Inc. Method and apparatus for routing
US6996789B2 (en) 2002-11-18 2006-02-07 Cadence Design Systems, Inc. Method and apparatus for performing an exponential path search
US7003752B2 (en) 2002-11-18 2006-02-21 Cadence Design Systems, Inc. Method and apparatus for routing
US7010771B2 (en) 2002-11-18 2006-03-07 Cadence Design Systems, Inc. Method and apparatus for searching for a global path
US7013445B1 (en) 2002-12-31 2006-03-14 Cadence Design Systems, Inc. Post processor for optimizing manhattan integrated circuits placements into non manhattan placements
US7013451B1 (en) 2002-01-22 2006-03-14 Cadence Design Systems, Inc. Method and apparatus for performing routability checking
US7024650B2 (en) 2000-12-06 2006-04-04 Cadence Design Systems, Inc. Method and apparatus for considering diagonal wiring in placement
US7036105B1 (en) 2002-01-22 2006-04-25 Cadence Design Systems, Inc. Integrated circuits with at least one layer that has more than one preferred interconnect direction, and method for manufacturing such IC's
US7047513B2 (en) 2002-11-18 2006-05-16 Cadence Design Systems, Inc. Method and apparatus for searching for a three-dimensional global path
US7055120B2 (en) 2000-12-06 2006-05-30 Cadence Design Systems, Inc. Method and apparatus for placing circuit modules
US7069530B1 (en) 2001-06-03 2006-06-27 Cadence Design Systems, Inc. Method and apparatus for routing groups of paths
US7073150B2 (en) 2000-12-07 2006-07-04 Cadence Design Systems, Inc. Hierarchical routing method and apparatus that use diagonal routes
US7080329B1 (en) 2002-01-22 2006-07-18 Cadence Design Systems, Inc. Method and apparatus for identifying optimized via locations
US7080342B2 (en) 2002-11-18 2006-07-18 Cadence Design Systems, Inc Method and apparatus for computing capacity of a region for non-Manhattan routing
US7089519B1 (en) 2002-12-31 2006-08-08 Cadence Design System, Inc. Method and system for performing placement on non Manhattan semiconductor integrated circuits
US7089524B1 (en) 2002-01-22 2006-08-08 Cadence Design Systems, Inc. Topological vias route wherein the topological via does not have a coordinate within the region
US7093221B2 (en) 2002-11-18 2006-08-15 Cadence Design Systems, Inc. Method and apparatus for identifying a group of routes for a set of nets
US7096449B1 (en) 2002-01-22 2006-08-22 Cadence Design Systems, Inc. Layouts with routes with different widths in different directions on the same layer, and method and apparatus for generating such layouts
US7107564B1 (en) 2001-06-03 2006-09-12 Cadence Design Systems, Inc. Method and apparatus for routing a set of nets
US7117468B1 (en) 2002-01-22 2006-10-03 Cadence Design Systems, Inc. Layouts with routes with different spacings in different directions on the same layer, and method and apparatus for generating such layouts
US7171635B2 (en) 2002-11-18 2007-01-30 Cadence Design Systems, Inc. Method and apparatus for routing
US7216308B2 (en) 2002-11-18 2007-05-08 Cadence Design Systems, Inc. Method and apparatus for solving an optimization problem in an integrated circuit layout
US7398498B2 (en) 2001-08-23 2008-07-08 Cadence Design Systems, Inc. Method and apparatus for storing routes for groups of related net configurations
US7480885B2 (en) 2002-11-18 2009-01-20 Cadence Design Systems, Inc. Method and apparatus for routing with independent goals on different layers
US7506295B1 (en) 2002-12-31 2009-03-17 Cadence Design Systems, Inc. Non manhattan floor plan architecture for integrated circuits
US7800236B1 (en) * 2007-02-28 2010-09-21 Integrated Device Technology, Inc. Semiconductor die and method for forming a semiconductor die having power and ground strips that are oriented diagonally

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5234775A (en) * 1975-09-12 1977-03-16 Tsuneo Washimi Colorific meter

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5234775A (en) * 1975-09-12 1977-03-16 Tsuneo Washimi Colorific meter

Cited By (39)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7024650B2 (en) 2000-12-06 2006-04-04 Cadence Design Systems, Inc. Method and apparatus for considering diagonal wiring in placement
US7055120B2 (en) 2000-12-06 2006-05-30 Cadence Design Systems, Inc. Method and apparatus for placing circuit modules
US7073150B2 (en) 2000-12-07 2006-07-04 Cadence Design Systems, Inc. Hierarchical routing method and apparatus that use diagonal routes
US6915501B2 (en) 2001-01-19 2005-07-05 Cadence Design Systems, Inc. LP method and apparatus for identifying routes
US7107564B1 (en) 2001-06-03 2006-09-12 Cadence Design Systems, Inc. Method and apparatus for routing a set of nets
US7069530B1 (en) 2001-06-03 2006-06-27 Cadence Design Systems, Inc. Method and apparatus for routing groups of paths
US6877146B1 (en) 2001-06-03 2005-04-05 Cadence Design Systems, Inc. Method and apparatus for routing a set of nets
US6957411B1 (en) 2001-06-03 2005-10-18 Cadence Design Systems, Inc. Gridless IC layout and method and apparatus for generating such a layout
US7398498B2 (en) 2001-08-23 2008-07-08 Cadence Design Systems, Inc. Method and apparatus for storing routes for groups of related net configurations
US7032201B1 (en) 2002-01-22 2006-04-18 Cadence Design Systems, Inc. Method and apparatus for decomposing a region of an integrated circuit layout
US7080329B1 (en) 2002-01-22 2006-07-18 Cadence Design Systems, Inc. Method and apparatus for identifying optimized via locations
US7117468B1 (en) 2002-01-22 2006-10-03 Cadence Design Systems, Inc. Layouts with routes with different spacings in different directions on the same layer, and method and apparatus for generating such layouts
US7114141B1 (en) 2002-01-22 2006-09-26 Cadence Design Systems, Inc. Method and apparatus for decomposing a design layout
US6898773B1 (en) 2002-01-22 2005-05-24 Cadence Design Systems, Inc. Method and apparatus for producing multi-layer topological routes
US7096449B1 (en) 2002-01-22 2006-08-22 Cadence Design Systems, Inc. Layouts with routes with different widths in different directions on the same layer, and method and apparatus for generating such layouts
US7013451B1 (en) 2002-01-22 2006-03-14 Cadence Design Systems, Inc. Method and apparatus for performing routability checking
US7020863B1 (en) 2002-01-22 2006-03-28 Cadence Design Systems, Inc. Method and apparatus for decomposing a region of an integrated circuit layout
US6957409B1 (en) 2002-01-22 2005-10-18 Cadence Design Systems, Inc. Method and apparatus for generating topological routes for IC layouts using perturbations
US6957408B1 (en) 2002-01-22 2005-10-18 Cadence Design Systems, Inc. Method and apparatus for routing nets in an integrated circuit layout
US7036105B1 (en) 2002-01-22 2006-04-25 Cadence Design Systems, Inc. Integrated circuits with at least one layer that has more than one preferred interconnect direction, and method for manufacturing such IC's
US7089524B1 (en) 2002-01-22 2006-08-08 Cadence Design Systems, Inc. Topological vias route wherein the topological via does not have a coordinate within the region
US6944841B1 (en) 2002-01-22 2005-09-13 Cadence Design Systems, Inc. Method and apparatus for proportionate costing of vias
US6938234B1 (en) 2002-01-22 2005-08-30 Cadence Design Systems, Inc. Method and apparatus for defining vias
US6898772B1 (en) 2002-01-22 2005-05-24 Cadence Design Systems, Inc. Method and apparatus for defining vias
US7010771B2 (en) 2002-11-18 2006-03-07 Cadence Design Systems, Inc. Method and apparatus for searching for a global path
US7216308B2 (en) 2002-11-18 2007-05-08 Cadence Design Systems, Inc. Method and apparatus for solving an optimization problem in an integrated circuit layout
US7480885B2 (en) 2002-11-18 2009-01-20 Cadence Design Systems, Inc. Method and apparatus for routing with independent goals on different layers
US7047513B2 (en) 2002-11-18 2006-05-16 Cadence Design Systems, Inc. Method and apparatus for searching for a three-dimensional global path
US7093221B2 (en) 2002-11-18 2006-08-15 Cadence Design Systems, Inc. Method and apparatus for identifying a group of routes for a set of nets
US6892369B2 (en) 2002-11-18 2005-05-10 Cadence Design Systems, Inc. Method and apparatus for costing routes of nets
US7080342B2 (en) 2002-11-18 2006-07-18 Cadence Design Systems, Inc Method and apparatus for computing capacity of a region for non-Manhattan routing
US6996789B2 (en) 2002-11-18 2006-02-07 Cadence Design Systems, Inc. Method and apparatus for performing an exponential path search
US6988257B2 (en) 2002-11-18 2006-01-17 Cadence Design Systems, Inc. Method and apparatus for routing
US7171635B2 (en) 2002-11-18 2007-01-30 Cadence Design Systems, Inc. Method and apparatus for routing
US7003752B2 (en) 2002-11-18 2006-02-21 Cadence Design Systems, Inc. Method and apparatus for routing
US7013445B1 (en) 2002-12-31 2006-03-14 Cadence Design Systems, Inc. Post processor for optimizing manhattan integrated circuits placements into non manhattan placements
US7089519B1 (en) 2002-12-31 2006-08-08 Cadence Design System, Inc. Method and system for performing placement on non Manhattan semiconductor integrated circuits
US7506295B1 (en) 2002-12-31 2009-03-17 Cadence Design Systems, Inc. Non manhattan floor plan architecture for integrated circuits
US7800236B1 (en) * 2007-02-28 2010-09-21 Integrated Device Technology, Inc. Semiconductor die and method for forming a semiconductor die having power and ground strips that are oriented diagonally

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